CY7C4255 datasheet(17/22 Pages) CYPRESS

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CY7C4255

CY7C4265

Document #: 38-06004 Rev. *C

Page 17 of 22

Width Expansion Configuration

The CY7C4255/65 can be expanded in width to provide word

widths greater than 18 in increments of 18. During width

expansion mode all control line inputs are common and all

flags are available. Empty (Full) flags should be created by

ANDing the Empty (Full) flags of every FIFO; the PAE and PAF

flags can be detected from any one device. This technique will

avoid reading data from, or writing data to the FIFO that is

“staggered” by one clock cycle due to the variations in skew

between RCLK and WCLK. Figure 1 demonstrates a 36-word

width by using two CY7C4255/65s.

Figure 1. Block Diagram of 8K x18/16K x 18 Synchronous FIFO Memory Used in a Width Expansion Configuration

WRITE CLOCK (WCLK)

WRITE ENABLE (WEN)

LOAD (LD)

PROGRAMMABLE(PAE)

HALF FULL FLAG (HF)

FULL FLAG (FF)

7C4255

7C4265

DATA IN (D)

RESET (RS)

READ CLOCK (RCLK)

READ ENABLE (REN)

OUTPUT ENABLE (OE)

PROGRAMMABLE (PAF)

EMPTY FLAG (EF)

DATA OUT (Q)

FIRST LOAD (FL)

WRITE EXPANSION IN (WXI)

READ EXPANSION IN (RXI)

7C4255

7C4265

CY7C4255 Datasheet(PDF) 17 Page - Cypress Semiconductor