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Table 22. Interrupt Status Register

Status Register Descriptions

Table 21. Real-Time Clock Register (continued)

BIT

NAME

DESCRIPTION

3:2

AM[1:0]

Alarm Control: The MAX35101 contains a time-of-day alarm. The alarm is activated when either

the AM1 or AM2 bits are set. When the RTC’s hours or minutes value increments to a value equal

to the alarm settings in Alarm registers, the AF bit in the Interrupt Status register is set and the

INT device pin is asserted (if enabled) and remains asserted until the Interrupt Status register is

accessed by the microprocessor with a read register command.

AM1

AM0

ALARM FUNCTION

No alarm

Alarm when minutes match

Alarm when hours match

Alarm when hours and minutes match

Watchdog Flag: This bit is set when the watchdog counter reaches zero. This bit must be written

to a zero to clear the bit. Writing this bit to a zero when the WDO pin is asserted low releases the

WDO pin to its inactive high-impedance state.

WD_EN

Watchdog Enable:

1 = Watchdog timer is enabled.

0 = Watchdog time is disabled, and the WDO pin is high impedance.

WRITE OPCODE

Read Only

READ OPCODE

FEh

FLASH STORED

DEFAULT VALUE

0000h

Bit

Name

TOF

LDO

TOF_

EVTMG

TEMP_

EVTMG

Bit

Name

FLASH

CAL

HALT

CSWI

INIT

POR

Note: This register is read only and bits are self-clearing upon a read to this register. See the Device Interrupt Operations section

for more information.

BIT

NAME

DESCRIPTION

Timeout: The TO bit is set if any one of the t1, t2, Hit1 through Hit6, or temperature measure-

ments do not occur within the associated timeout window.

Alarm Flag: Set when the RTC’s hours or minutes value increments to a value equal to the alarm

settings in Alarm registers.

Reserved

MAX35101

Time-to-Digital Converter with Analog Front-End

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