64/256/512/1K/2K/4K/8K x 9 Synchronous FIFOs
CY7C4421/4201/4211/4221
CY7C4231/4241/4251
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
, CA 95134
•
408-943-2600
Document #: 38-06016 Rev. *C
Revised August 2, 2005
Features
• High-speed, low-power, First-In, First-Out (FIFO)
memories
— 64 × 9 (CY7C4421)
— 256 × 9 (CY7C4201)
— 512 × 9 (CY7C4211)
— 1K × 9 (CY7C4221)
— 2K × 9 (CY7C4231)
— 4K × 9 (CY7C4241)
— 8K × 9 (CY7C4251)
• High-speed 100-MHz operation (10 ns Read/Write cycle
time)
•Low power (ICC = 35 mA)
• Fully asynchronous and simultaneous Read and Write
operation
• Empty, Full, and Programmable Almost Empty and
Almost Full status flags
• TTL-compatible
• Expandable in width
• Output Enable (OE) pin
• Independent Read and Write enable pins
• Center power and ground pins for reduced noise
• Width-expansion capability
• Space saving 7 mm × 7 mm 32-pin TQFP
• Pin-compatible and functionally equivalent to
IDT72421, 72201, 72211, 72221, 72231, and 72241
• Pb-Free Packages Available
Functional Description
The CY7C42X1 are high-speed, low-power FIFO memories
with clocked Read and Write interfaces. All are 9 bits wide. The
CY7C42X1 are pin-compatible to IDT722X1. Programmable
features include Almost Full/Almost Empty flags. These FIFOs
provide solutions for a wide variety of data buffering needs,
including high-speed data acquisition, multiprocessor inter-
faces, and communications buffering.
These FIFOs have 9-bit input and output ports that are
controlled by separate clock and enable signals. The input port
is controlled by a free-running clock (WCLK) and two
Write-enable pins (WEN1, WEN2/LD).
When WEN1 is LOW and WEN2/LD is HIGH, data is written
into the FIFO on the rising edge of the WCLK signal. While
WEN1, WEN2/LD is held active, data is continually written into
the FIFO on each WCLK cycle. The output port is controlled in
a similar manner by a free-running Read clock (RCLK) and two
Read-enable pins (REN1, REN2). In addition, the CY7C42X1
has an output enable pin (OE). The Read (RCLK) and Write
(WCLK) clocks may be tied together for single-clock operation
or the two clocks may be run independently for asynchronous
Read/Write applications. Clock frequencies up to 100 MHz are
achievable.
Depth expansion is possible using one enable input for system
control, while the other enable is controlled by expansion logic
to direct the flow of data.
Logic Block Diagram
Pin Configurations
THREE-STATE
OUTPUT REGISTER
Read
CONTROL
FLAG
LOGIC
Write
CONTROL
Write
POINTER
Read
POINTER
RESET
LOGIC
INPUT
REGISTER
FLAG
PROGRAM
REGISTER
D0- 8
RCLK
EF
PAE
PAF
Q0- 8
WEN1
WCLK
RS
OE
Dual Port
RAM Array
64 x 9
8k x 9
WEN2/LD
REN1 REN2
FF
1
2
3
4
5
6
7
8
D1
D0
RCLK
GND
PAF
PAE
REN1
REN2
17
18
19
20
21
22
23
24
14 15 16
910 11 12 13
31 30
32
29 28 27
25
26
VCC
WCLK
WEN2/LD
Q8
Q7
Q6
Q5
WEN1
TQFP
Top View
PLCC
D1
D0
RCLK
VCC
GND
WCLK
WEN2/LD
Q8
Q7
PAF
PAE
5
6
7
8
9
10
11
12
13
REN1
OE
REN2
4 3 2 1
3130
32
21
22
23
24
27
28
29
25
26
14151617181920
Q6
Q5
WEN1
RS
Top View
CY7C4421/4201/4211/4221 CY7C4231/4241/425164/256/512/1K/2K/4K/8K x 9 Synchronous FIFOs
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