CY7C4801-35AI datasheet(9/23 Pages) CYPRESS

Part #	CY7C4801-35AI

Description	256/512/1K/2K/4K/8K x9 x2 Double Sync FIFOs

PDF	23 Pages

Scroll/Zoom	100%

Manufacturer	CYPRESS [Cypress Semiconductor]

Direct Link	http://www.cypress.com

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9 / 23 page

CY7C4801/4811/4821

CY7C4831/4841/4851

Document #: 38-06005 Rev. *A

Page 9 of 23

Notes:

16. When tSKEW1 > minimum specification, tFRL (maximum) = tCLK + tSKEW1. When tSKEW1 < minimum specification, tFRL (maximum) = either 2*tCLK + tSKEW1 or tCLK + tSKEW1.

The Latency Timing applies only at the Empty Boundary (EFA, EFB= LOW).

17. The first word is available the cycle after (EFA, EFB) goes HIGH, always.

Switching Waveforms (continued)

(RENB1,RENB2)

D0 (FIRSTVALIDWRITE)

First Data Word Latency after Reset with Simultaneous Read and Write

tSKEW1

WENA1(WENB1)

WCLKA,WCLKB

QA0 −QA8

EFA(EFB)

RENA1, RENA2

OEA(OEB)

tOE

tENS

tOLZ

tDS

RCLKA(RCLKB)

tREF

tFRL

DA0−DA8

48X1–9

WENA2(WENB2)

(if applicable)

(DB0−DB8)

(QB0−QB8)

[16]

[17]

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