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CY7C4801/4811/4821
CY7C4831/4841/4851
Document #: 38-06005 Rev. *A
Page 18 of 23
Width Expansion Configuration
Word width may be increased simply by connecting the corre-
sponding input control signals of FIFOs A and B. A composite
flag should be created for each of the end-point status flags
EFA and EFB, also FFA and FFB. The partial status flags
PAEA, PAFB, PAFA, PAFB can be detected from any one de-
vice. Figure 3 demonstrates an 18-bit word width using the two
FIFOs contained in one CY7C4801/4811/4821/4831/4841
/4851. Any word width can be attained by adding additional
CY7C4801/4811/4821/4831/4841/4851s.
When the CY7C4801/4811/4821/4831/4841/4851 is in a
Width Expansion Configuration, the Read Enable 2 (RENA2
and RENB2) control unputs can be grounded (see Figure 3).
In
this
configuration,
the
Write
Enable
2/Load
(WENA2/LDA,WENB2/LDB) pins are set LOW at Reset so
that the pin operates as a control to load and read the program-
mable flag offsets.
Figure 3. Block Diagram of two FIFOs contained in one CY7C4801/4811/4821/4831/4841/4851 configured for an 18-bit
width-expansion.
WRITE ENABLE
WENA
(RENA2)
48X1–17
FF
EF
WCLKA
WRITE ENABLE 2/LOAD
WEN2/LD
FULL FLAG
FFA
9
18
RESET (RSA)
9
RESET(RSB)
RCLKB
READ ENABLE
RENB1
OUTPUT ENABLE
OEB
EMPTY FLAG
EFA
9
9
18
Read Enable 2
EFB
FFB
Read Enable 2 (RENB2)
RAM ARRAY A
RAM ARRAY B
256 x 9
512 x 9
1024 x 9
2048 x 9
4096 x 9
8192 x 9
256 x 9
512 x 9
1024 x 9
2048 x 9
4096 x 9
8192 x 9
RCLKA
WCLKB
WRITECLOCK
READCLOCK
RENA1
WENB1
OEA
WENB2/LDB
RESET
9
D0−D17
Q0−Q17
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