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Preliminary Technical Data

AD7357

Rev. PrD | Page 5 of 17

TIMING SPECIFICATIONS

VDD = 2.5 +/-10%V, VDRIVE = 2.5 V to 3.3 +10% V, internal reference = 2.048 V, TA = TMAX to TMIN1, unless otherwise noted.

Table 2.

Parameter

Limit at TMIN, TMAX

Unit

Description

fSCLK

kHz min

MHz max

tCONVERT

t2 +15.5 × tSCLK

ns max

14 bit resolution, tSCLK = 1/fSCLK

tQUIET

ns min

Minimum time between end of serial read and next falling edge of CS

ns min

CS to SCLK setup time

TBD

ns max

Delay from CS until DOUTA and DOUTB are three-state disabled

t42

TBD

ns max

Data access time after SCLK falling edge

0.40 tSCLK

ns min

SCLK low pulse width

0.40 tSCLK

ns min

SCLK high pulse width

TBD

ns min

SCLK to data valid hold time

TBD

ns max

CS rising edge to DOUTA, DOUTB, high impedance

TBD

ns min

CS rising edge to falling edge pulse width

t10

TBD

ns min

SCLK falling edge to DOUTA, DOUTB, high impedance

TBD

ns max

SCLK falling edge to DOUTA, DOUTB, high impedance

Latency

1 Conversion Latency

1 Temperature ranges are as follows: Y Grade: −40°C to +125°C, B Grade: −40°C to +85°C.

2 The time required for the output to cross 0.4 V or 2.4 V.

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