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AD7352 Datasheet(PDF) 15 Page - Analog Devices

Part # AD7352
Description  Differential Input,Dual,Simultaneous Sampling, 4.25 MSPS, 14-Bit, SAR ADC
PDF  17 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD7352 Datasheet(HTML) 15 Page - Analog Devices

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Preliminary Technical Data
AD7357
Rev. PrD | Page 15 of 17
POWER-UP TIMES
The AD7357 has two power-down modes, partial power-down
and full power-down, which are described in detail in the
previous sections. This section deals with the power-up time
required when coming out of either of these modes.
To power up from partial power-down mode, one dummy cycle
is required. The device is fully powered up after approximately
TBD µs from the falling edge of CS has elapsed. Once the
partial power-up time has elapsed, the ADC is fully powered up
and the input signal is acquired properly. The quiet time, tQUIET,
must still be allowed from the point where the bus goes back
into three-state after the dummy conversion to the next falling
edge of CS.
To power up from full power-down, approximately TBD μs
should be allowed from the falling edge of CS, shown in Figure
18 as tPOWER-UP2.
Note that during power-up from partial power-down mode, the
track-and-hold, which is in hold mode while the part is powered
down, returns to track mode after the first SCLK edge that the
part receives after the falling edge of CS.
When power supplies are first applied to the AD7357, the ADC
can power up in either of the power-down modes or in normal
mode. Because of this, it is best to allow a dummy cycle to
elapse to ensure that the part is fully powered up before
attempting a valid conversion. Likewise, if the part is to be kept
in partial power-down mode immediately after the supplies are
applied, then two dummy cycles must be initiated. The first
dummy cycle must hold CS low until after the 10th SCLK falling
edge; in the second cycle, CS must be brought high between the
second and 10th SCLK falling edges (see Figure 15).
Alternatively, if the part is to be placed into full power-down
mode when the supplies are applied, three dummy cycles must
be initiated. The first dummy cycle must hold CS low until after
the 10th SCLK falling edge; the second and third dummy cycles
place the part into full power-down mode (see Figure 17). See
the Modes of Operation section.



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