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CY29658
Document #: 38-07478 Rev. **
Page 5 of 7
frefDC
Input Duty Cycle
40
–
60
%
VPP
Peak-Peak Input Voltage
LVPECL
500
–
1000
mV
VCMR
Common Mode Range[8]
LVPECL
1.2
–
VDD - 0.9
V
fMAX
Maximum Output Frequency
÷2 Output
100
–
200
MHz
÷4 Output
50
–
125
DC
Output Duty Cycle
45
–
55
%
tr , tf
Output Rise/Fall times
0.55V to 2.4V
0.1
–
1.0
ns
t(φ)
Propagation Delay (static phase
offset)
PCLK to FB_IN, same VDD
–200
–
225
ps
tPD
Propagation Delay (PLL and
divider bypass)
PCLK to Q0 – Q9
BYPASS# = 0
3.6
4.8
6.0
ns
tsk(O)
Output-to-Output Skew
–
–
150
ps
tPLZ, HZ
Output Disable Time
–
–
6
ns
tPZL, ZH
Output Enable Time
–
–
6
ns
BW
PLL Closed Loop Bandwidth
(–3dB)
÷2 Feedback
–
1.9 – 2.2
–
MHz
÷4 Feedback
–
1.8 – 2.1
–
tJIT(CC)
Cycle-to-Cycle Jitter
–
–
100
ps
tJIT(PER)
Period Jitter
–
–
75
ps
tJIT(φ)
I/O Phase Jitter
I/O same VDD
–
–
150
ps
tLOCK
Maximum PLL Lock Time
–
–
1
ms
AC Electrical Specifications (VDD = 3.3V ± 5%, TA = –40°C to +85°C) (continued)
[7]
Parameter
Description
Condition
Min.
Typ.
Max.
Unit
Differential
Pulse
Generator
Z = 50 ohm
Zo = 50 ohm
Zo = 50 ohm
VTT
RT = 50 ohm
Zo = 50 ohm
RT = 50 ohm
VTT
Figure 1. AC Test Reference for VDD = 3.3V / 2.5V
(φ)
PECL_CLK
PECL_CLK
V PP
FB_IN
VCMR
VDD
GND
VDD/2
t
Figure 2. Propagation Delay t(
φ), Static Phase Offset
PECL_CLK
PECL_CLK
V PP
Qn
VCMR
VDD
GND
VDD/2
t
PD
Figure 3. Propagation Delay tPD, PLL Bypass
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