2.5V or 3.3V 200-MHz 10-Output Zero Delay Buffer
CY29658
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
, CA 95134
•
408-943-2600
Document #: 38-07478 Rev. **
Revised May 14, 2003
Features
• Output frequency range: 50 MHz to 200 MHz
• Input frequency range: 50 MHz to 200 MHz
• 2.5V or 3.3V operation
• Ten clock outputs: drive up to 20 clock lines
• One Feedback output
• LVPECL reference clock input
• 150-ps max output-output skew
• Phase-locked loop (PLL) bypass mode
• Spread Aware™
• Output enable/disable
• Pin-compatible with MPC9658 and MPC958
• Industrial temperature range: –40°C to +85°C
• 32-Pin 1.0mm TQFP package
Description
The CY29658 is a low-voltage high-performance 200-MHz
PLL-based zero delay buffer designed for high-speed clock
distribution applications. The CY29658 features an LVPECL
reference clock input and provides ten outputs plus one
feedback output. VCO output divides by two or four per
VCO_SEL
setting
(see
Function
Table).
Each
LVCMOS-compatible output can drive 50
Ω series- or
parallel-terminated transmission lines. For series-terminated
transmission lines, each output can drive one or two traces
giving the device an effective fanout of 1:20.
The PLL is ensured stable given that the VCO is configured to
run between 200 MHz to 500 MHz. This allows a wide range
of output frequencies from 50 MHz to 200 MHz. For normal
operation, the external feedback input, FB_IN, is connected to
the feedback output, FB_OUT. The internal VCO is running at
multiples of the input reference clock set by the feedback
divider (see Frequency Table).
When PLL_EN is LOW, PLL is bypassed and the reference
clock directly feeds the output dividers. This mode is fully static
and the minimum input clock frequency specification does not
apply. When BYPASS# is set LOW, PLL and output dividers
are bypassed resulting in a 1:11 LVPECL to LVCMOS high
performance fanout buffer. For normal PLL operation, both
PLL_EN and BYPASS# are set HIGH.
Block Diagram
Pin Configuration
C Y 29658
Q2
V DDQ
Q3
VSS
Q4
V DDQ
Q5
VSS
AVD D
FB _ IN
BYPASS#
P LL_E N
MR /O E#
PEC L _ C LK
P E C L_C LK #
AVSS
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
Phase
Detector
LPF
VCO
200-480M
/2
/2
PECL_CLK
PECL_CLK#
FB_IN
VCO_SEL
BYPASS#
MR/OE#
PLL_EN
FB_OUT
Q(0:8)
Q9
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