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AD4692BCPZ Datasheet(PDF) 44 Page - Analog Devices |
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AD4692BCPZ Datasheet(HTML) 44 Page - Analog Devices |
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44 / 81 page ![]() Data Sheet AD4691/AD4692 DIGITAL INTERFACE analog.com Rev. 0 | 44 of 81 CRC Error Detection The AD4691/AD4692 include SPI transmission error detection for register reads and writes based on the following CRC-8 polynomial: x8+x2+x+1 (5) The CRC is enabled by setting the CRC_EN_A and CRC_EN_B bit fields to 0x1 and 0x2 in the same SPI frame, respectively. Both bit fields must be written in the same SPI frame to prevent SPI transaction errors from inadvertently enabling or disabling CRC. When the CRC is enabled an 8-bit checksum code is appended to each REG_DATA packet in the data phase, as shown in Figure 74. The checksum calculator applies the CRC-8 polynomial to the incoming and outgoing REG_DATA packets, allowing the AD4691/ AD4692 to detect transmission errors from the host and vice versa. Figure 74 and Figure 75 shows the expected CRC checksum code format for single or multiple register writes and reads per SPI frame. When CRC is enabled, the AD4691/AD4692 send checksum codes to the digital host via SDO and validate checksum codes sent by the digital host via SDI. If the incoming checksum does not match the expected value, the AD4691/AD4692 assume the transmission was corrupted; therefore, the internal registers do not update their values, and the CRC_ERROR bit in the SPI_STATUS register is asserted. The host software should periodically check the CRC_ERROR bit to detect the occurrence of corrupted data trans- missions and resulting unexpected device configuration settings. Table 22 summarizes the data and seed values for the checksum calculation for all possible register write and read transactions. The checksum calculation is seeded by a nonzero value to detect if the SDI input is stuck low. The seed value is 0xA5 for the first register write or read in the SPI frame. For bulk transactions, the checksum for each subsequent register is seeded with the MSByte of the address of that register (for example, 0x0025 for STD_SEQ_CONFIG, and so on). Table 22. CRC Calculator Seed and Data Values Command CRC Source First CRC Subsequent CRCs Seed Input Data Input Seed Data Source Write SDI (from host) 0xA5 R/W, REG_ADDR, REG_DATA Current start address REG_DATA SDO (to host) R/W, REG_ADDR, REG_DATA Current start address REG_DATA Read SDI (from host) 0xA5 R/W, REG_ADDR, PAD- DING Not required, send pad- ding data SDO (to host) R/W, REG_ADDR, REG_DATA Current start address REG_DATA |
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