W158
Document #: 38-07164 Rev. *A
Page 5 of 13
Table 5. Clock Enable Configuration[9, 10, 11, 12, 13, 14]
CPU_STOP# PWRDWN# PCI_STOP#
CPU
CPUdiv2
IOAPIC
3V66
PCI
PCI_F
REF,
48MHz
OSC.
VCOs
X
0
X
LOW
LOW
LOW
LOW
LOW
LOW
LOW
OFF
OFF
0
1
0
LOW
ON
ON
LOW
LOW
ON
ON
ON
ON
0
1
1
LOW
ON
ON
LOW
ON
ON
ON
ON
ON
1
1
0
ON
ON
ON
ON
LOW
ON
ON
ON
ON
1
1
1
ON
ON
ONON
ON
ON
ONONON
Table 6. Power Management State Transition[15, 16]
Signal
Signal State
Latency
No. of rising edges of PCI Clock
CPU_STOP#
0 (disabled)
1
1 (enabled)
1
PCI_STOP#
0 (disabled)
1
1 (enabled)
1
PWRDWN#
1 (normal operation)
3 ms
0 (power down)
2 max.
Timing Diagrams
CPU_STOP# Timing Diagram[17, 18, 19, 20, 21, 22]
Notes:
9.
LOW means outputs held static LOW as per latency requirement below.
10. ON means active.
11. PWRDWN# pulled LOW, impacts all outputs including REF and 48-MHz outputs.
12. All 3V66 as well as all CPU clocks stop cleanly when CPU_STOP# is pulled LOW.
13. CPUdiv2, IOAPIC, REF, 48MHz signals are not controlled by the CPU_STOP# functionality and are enabled in all conditions except PWRDWN#=LOW.
14. An “x” indicates a “don’t care” condition.
15. Clock on/off latency is defined in the number of rising edges of the free-running PCI clock between when the clock disable goes LOW/HIGH to when the first
valid clock comes out of the device.
16. Power up latency is from when PWRDWN# goes inactive (HIGH) to when the first valid clocks are driven from the device.
17. All internal timing is referenced to the CPU clock.
18. The internal label means inside the chip and is a reference only. This, in fact, may not be the way that the control is designed.
19. CPU_STOP# signal is an input signal that must be made synchronous to free-running PCI_F.
20. 3V66 clocks also stop/start before.
21. PWRDWN# and PCI_STOP# are shown in a HIGH state.
22. Diagrams shown with respect to 133 MHz. Similar operation when CPU clock is 100 MHz.
CPU
PCI
CPU_STOP#
PCI_STOP#
PWRDWN#
3V66
(internal)
HI
HI
CPU
(external)
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