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W158
Document #: 38-07164 Rev. *A
Page 6 of 13
PCI_STOP# Timing Diagram[18, 22, 23, 24, 25, 26]
PWRDWN# Timing Diagram[18, 22, 23, 27, 28]
Notes:
23. All internal timing is referenced to the CPU clock.
24. PCI_STOP# signal is an input signal that must be made synchronous to PCI_F output.
25. All other clocks continue to run undisturbed.
26. PWRDWN# and CPU_STOP# are shown in a HIGH state.
27. PWRDWN is an asynchronous input and metastable conditions could exist. This signal must be synchronized.
28. The shaded Sections on the VCO and the Crystal signals indicate an active clock.
Timing Diagrams (continued)
CPU
PCI
PCI_STOP#
PWRDWN#
PCI_F
(external)
HI
HI
(internal)
PCI
(external)
CPU_STOP#
CPU
PCI
PWRDWN#
VCO
Crystal
PCI
CPU
(internal)
(internal)
(external)
(external)
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