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3.3V, 150MHz, Multi-Output Zero Delay Buffer
Cypress Semiconductor Corporation
http://www.cypress.com
Document#: 38-07091 Rev. *B
12/26/2002
Page 2 of 8
Z9975
Block Diagram
Fig.1
VDD
VDD
VDD
VDD
VDD
5
5
4
250K
1
0
0
1
Divide by
1, 2 & 4
C
/2
/4
Divide by
2, 4 & 6
C
/2
/4
/6
0
1
0
1
0
1
Div. by 2
C
/2
5
5
4
1
4
5
5
A
B
AND
Gate
A
B
Y
A
B
Y
250K
PLL
Ref-in
VCO-out
Feedback
250K
250K
0
1
0
1
250K
250K
250K
250K
250K
250K
250K
250K
250K
TCLK0
TCLK1
FB_In
PLL_EN
VCO_sel0
QFB
Qa(0:4)
Qb(0:4)
Qc(0:3)
MR#
fsela
TCLK_sel
OE
fselc
fselb
fselFB1
fselFB0
Reset#
Reset#
Reset#
PLLinit#
Y
AND
Gate
AND
Gate
VCO_Sel1
VSS
/1
250K