3.3V, 150MHz, Multi-Output Zero Delay Buffer
Cypress Semiconductor Corporation
http://www.cypress.com
Document#: 38-07091 Rev. *B
12/26/2002
Page 3 of 8
Z9975
Output Frequency Selection Table (VCO_Sel1 = 0)
Inputs
Outputs
VCO_sel0
fsela
fselb
fselc
Qa(0:4)
Qb(0:4)
Qc(0:3)
0
0
0
0
VCO/4
VCO/4
VCO/8
0
0
0
1
VCO/4
VCO/4
VCO/12
0
0
1
0
VCO/4
VCO/8
VCO/8
0
0
1
1
VCO/4
VCO/8
VCO/12
0
1
0
0
VCO/8
VCO/4
VCO/8
0
1
0
1
VCO/8
VCO/4
VCO/12
0
1
1
0
VCO/8
VCO/8
VCO/8
0
1
1
1
VCO/8
VCO/8
VCO/12
1
0
0
0
VCO/8
VCO/8
VCO/16
1
0
0
1
VCO/8
VCO/8
VCO/24
1
0
1
0
VCO/8
VCO/16
VCO/16
1
0
1
1
VCO/8
VCO/16
VCO/24
1
1
0
0
VCO/16
VCO/8
VCO/16
1
1
0
1
VCO/16
VCO/8
VCO/24
1
1
1
0
VCO/16
VCO/16
VCO/16
1
1
1
1
VCO/16
VCO/16
VCO/24
Table 2
Output Frequency Selection Table (VCO_Sel1 = 1)
Inputs
Outputs
VCO_sel0
fsela
fselb
fselc
Qa(0:4)
Qb(0:4)
Qc(0:3)
0
0
0
0
VCO/2
VCO/2
VCO/4
0
0
0
1
VCO/2
VCO/2
VCO/6
0
0
1
0
VCO/2
VCO/4
VCO/4
0
0
1
1
VCO/2
VCO/4
VCO/6
0
1
0
0
VCO/4
VCO/2
VCO/4
0
1
0
1
VCO/4
VCO/2
VCO/6
0
1
1
0
VCO/4
VCO/4
VCO/4
0
1
1
1
VCO/4
VCO/4
VCO/6
1
0
0
0
VCO/4
VCO/4
VCO/8
1
0
0
1
VCO/4
VCO/4
VCO/12
1
0
1
0
VCO/4
VCO/8
VCO/8
1
0
1
1
VCO/4
VCO/8
VCO/12
1
1
0
0
VCO/8
VCO/4
VCO/8
1
1
0
1
VCO/8
VCO/4
VCO/12
1
1
1
0
VCO/8
VCO/8
VCO/8
1
1
1
1
VCO/8
VCO/8
VCO/12
Table 3
Pin Description
PIN No.
Pin Name
I/O
Description
2
MR#
I
Active low Master Reset pin. It has a 250K
Ω internal pull-up. When forced low, all outputs
are Tri-stated (high impedance) and internal ratio dividers are reset.
3
OE
I
Active high Output Enable pin. It has a 250K
Ω internal pull-up. When forced low, Qa(0:4),
Qb(0:4), and Qc(0:3) outputs are stopped in a low state. QFB is not effected by this signal.
7,4, 5
Fsel(a,b,c)
I
Input select pins for setting the output dividers at Qa(0:4), Qb(0:4), and Qc(0:3)
respectively. Each pin has an internal 250K
Ω pull-down. See table 2, page 3.
6
PLL_EN
I
Input pin for bypassing the PLL. It has an internal 250K
Ω pull-up. When forced low,
the input reference clock (applied at TCLK0, or TCLK1) bypasses the PLL and drives the
dividers, typically for device testing. In this case, the PLL is disabled.
8
TCLK_sel
I
Input pin for selecting TCLK0 or TCLK1 as input reference. When TCLK_sel = 0, TCLK0 is
selected, when TCLK_sel = 1, TCLK1 is selected. This pin has a 250K
Ω internal pull-down.
9,10
TCLK(0:1)
I
Input pins for applying a reference clock to the PLL. The active input is selected by
TCLK_sel, pin# 8. TCLK0 has a 250K
Ω internal pull-down. TCLK1 has a 250KΩ internal
pull-up.
14, 20
FselFB(0:1)
I
Input select pins for setting the Feedback divide ratio at QFB output, pin#29. See table 1,
page1. Each of these pins has a 250K
Ω internal pull-down.
25,23,21,
18,16
Qa(0:4)
O
High drive, Low Voltage CMOS, Output clock buffers, Bank Qa. Their divide ratio is
programmed by fsela, pin#7.
29
QFB
O
Low Voltage CMOS output feedback clock to the internal PLL. The divide ratio for this
output is set by fsleFB(0:1). A delay capacitor, or trace may be applied to this pin in order
to control the Input Reference/Output Banks phase relationship.
31
FB_In
I
Feedback input pin. Typically connects to the QFB output for accessing the Feedback to
the PLL. It has a 250K
Ω internal pull-up.
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