M25PE10-VMP6TP datasheet(27/64 Pages) NUMONYX

27 / 64 page

M25PE20, M25PE10

Instructions

27/64

6.4

Read Status Register (RDSR)

The Read Status Register (RDSR) instruction allows the Status Register to be read. The

Status Register may be read at any time, even while a Program, Erase or Write cycle is in

progress. When one of these cycles is in progress, it is recommended to check the Write In

Progress (WIP) bit before sending a new instruction to the device. It is also possible to read

the Status Register continuously, as shown in Figure 11.

The status bits of the Status Register are as follows:

6.4.1

WIP bit

The Write In Progress (WIP) bit indicates whether the memory is busy with a Write, Program

or Erase cycle. When set to ‘1’, such a cycle is in progress, when reset to ‘0’ no such cycle is

in progress.

6.4.2

WEL bit

The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.

When set to ‘1’ the internal Write Enable Latch is set, when set to ‘0’ the internal Write

Enable Latch is reset and no write, program or erase instruction is accepted.

6.4.3

BP1, BP0 bits

The Block Protect (BP1, BP0) bits are non-volatile. They define the size of the area to be

software protected against Program and Erase instructions. These bits are written with the

Write Status Register (WRSR) instruction. When one or both of the Block Protect (BP1,

BP0) bits is set to ‘1’, the relevant memory area (as defined in Table 3) becomes protected

against Page Program (PP), Page Erase (PE), Sector Erase (SE) and SubSector Erase

(SSE) instructions. The Block Protect (BP1, BP0) bits can be written provided that the

Hardware Protected mode has not been set. The Bulk Erase (BE) instruction is executed if,

and only if:

●

all Block Protect (BP1, BP0) bits are 0

●

the Lock Register protection bits are not all set to ‘1’.

6.4.4

SRWD bit

The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write

Protect (W) signal. When the Status Register Write Disable (SRWD) bit is set to ‘1’, and

Write Protect (W) is driven Low, the non-volatile bits of the Status Register (SRWD, BP1,

BP0) become read-only bits. In such a state, as the Write Status Register (WRSR)

instruction is no longer accepted for execution, the definition of the size of the Write

Protected area cannot be further modified.

Table 9.

Status Register format(1) (2)

SRWD = Status Register Write Protect bit; BP0, BP1 = block protect bits (only available with T9HX).

The BP bits and the SRWD bit exist only in the T9HX process.

SRWD

BP1

BP0

WEL(3)

WEL (Write Enable Latch) and WIP (Write In Progress) are volatile read-only bits (WEL is set and reset by

specific instructions; WIP is automatically set and reset by the internal logic of the device).

WIP(3)

M25PE10-VMP6TP Datasheet(PDF) 27 Page - Numonyx B.V

M25PE10-VMP6TP Datasheet(HTML) 27 Page - Numonyx B.V

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64

Datasheet Download

Link URL