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S3029 Datasheet(PDF) 1 Page - Applied Micro Circuits Corporation

Part # S3029
Description  SONET/SDH/ATM 155 MBIT/S QUAD TRANSCEIVER
PDF  11 Pages
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Manufacturer  AMCC [Applied Micro Circuits Corporation]
Direct Link  http://www.amcc.com
Logo AMCC - Applied Micro Circuits Corporation

S3029 Datasheet(HTML) 1 Page - Applied Micro Circuits Corporation

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S3029
SONET/SDH/ATM 155 MBIT/S QUAD TRANSCEIVER
February 19, 1999 / Revision B
BiCMOS PECL CLOCK GENERATOR
DEVICE
SPECIFICATION
SONET/SDH/ATM 155 MBIT/S QUAD TRANSCEIVER
S3029
®
FEATURES
•
Complies with ANSI, Bellcore, and ITU-T
specifications for jitter tolerance, jitter generation
•
Five on-chip high frequency PLLs with
internal loop filters for clock recovery
•
Supports clock recovery for STS-3/STM-1
(155.52 Mbit/s) NRZ data
•
Clock Multiplier PLL for transmit clock
generation
•
19.44 or 51.84 MHz reference frequency
•
Lock detect—monitors run length and
frequency
•
Low-jitter differential interface
•
3.3V supply
•
Available in a 64-pin TQFP package
•
Compatible with IgT WAC-413 ATM Quad-
UNI processor
GENERAL DESCRIPTION
The function of the S3029 clock synthesis and recov-
ery unit is to derive high speed timing signals for
SONET/SDH-based equipment. The S3029 is imple-
mented using AMCC’s proven Phase Locked Loop
(PLL) technology.
The S3029 receives four STS-3/STM-1 scrambled NRZ
signals and recovers the clock from the data and
generates a 155 MHz transmit clock. The chip out-
puts a differential PECL bit clock and retimed data.
Figure 1 shows a typical network application.
The S3029 utilizes five on-chip PLLs which consist of
a phase detector, a loop filter, and a voltage con-
trolled oscillator (VCO). The phase detector
compares the phase relationship between the VCO
output and the serial data input. A loop filter converts
the phase detector output into a smooth DC voltage,
and the DC voltage is input to the VCO whose fre-
quency is varied by this voltage. A block diagram is
shown in Figure 2. There is a single clock multiplier
PLL which generates a 155 MHz transmit clock from
a 19.44 or 51.84 MHz input.
Figure 1. System Block Diagram
155 Mbp/s
Network
Interface Processor
155 Mbp/s
Network
Interface Processor
155 Mbp/s
Network
Interface Processor
155 Mbp/s
Network
Interface Processor
TXCLK
TXDATA
RXDATA
RXCLK
Optical
Transceiver
Optical
Transceiver
S3029
S3029
Optical
Transceiver
Optical
Transceiver
RX
RX
RX
RX
TXCLK
TXDATA
RXDATA
RXCLK
TXCLK
TXDATA
RXDATA
RXCLK
TXCLK
TXDATA
RXDATA
RXCLK
155 Mbp/s
Network
Interface Processor
155 Mbp/s
Network
Interface Processor
155 Mbp/s
Network
Interface Processor
155 Mbp/s
Network
Interface Processor
TXCLK
TXDATA
RXDATA
RXCLK
Optical
Transceiver
Optical
Transceiver
Optical
Transceiver
Optical
Transceiver
RX
RX
RX
RX
TXCLK
TXDATA
RXDATA
RXCLK
TXCLK
TXDATA
RXDATA
RXCLK
TXCLK
TXDATA
RXDATA
RXCLK


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