TMS320DM641 datasheet(131/179 Pages) TI

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Inter-Integrated Circuit (I2C)

131

June 2003 − Revised October 2005

SPRS222E

4.10.3

I2C Electrical Data/Timing

4.10.3.1 Inter-Integrated Circuits (I2C) Timing

Table 4−36. Timing Requirements for I2C Timings† (see Figure 4−38)

−400

−500

−600

NO.

STANDARD

MODE

FAST

MODE

UNIT

MIN

MAX

MIN

MAX

tc(SCL)

Cycle time, SCL

2.5

µs

tsu(SCLH-SDAL)

Setup time, SCL high before SDA low (for a repeated START

condition)

4.7

0.6

µs

th(SCLL-SDAL)

Hold time, SCL low after SDA low (for a START and a repeated

START condition)

0.6

µs

tw(SCLL)

Pulse duration, SCL low

4.7

1.3

µs

tw(SCLH)

Pulse duration, SCL high

0.6

µs

tsu(SDAV-SDLH) Setup time, SDA valid before SCL high

250

100‡

th(SDA-SDLL)

Hold time, SDA valid after SCL low (For I2C bus™ devices)

0§

0.9¶

µs

tw(SDAH)

Pulse duration, SDA high between STOP and START conditions

4.7

1.3

µs

tr(SDA)

Rise time, SDA

1000

20 + 0.1Cb#

300

tr(SCL)

Rise time, SCL

1000

20 + 0.1Cb#

300

tf(SDA)

Fall time, SDA

300

20 + 0.1Cb#

300

tf(SCL)

Fall time, SCL

300

20 + 0.1Cb#

300

tsu(SCLH-SDAH) Setup time, SCL high before SDA high (for STOP condition)

0.6

µs

tw(SP)

Pulse duration, spike (must be suppressed)

Cb#

Capacitive load for each bus line

400

† The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered down.

‡ A Fast-mode I2C-bus™ device can be used in a Standard-mode I2C-bus™ system, but the requirement tsu(SDA−SCLH) ≥ 250 ns must then be met.

This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period

of the SCL signal, it must output the next data bit to the SDA line tr max + tsu(SDA−SCLH) = 1000 + 250 = 1250 ns (according to the Standard-mode

I2C-Bus Specification) before the SCL line is released.

§ A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the undefined

region of the falling edge of SCL.

¶ The maximum th(SDA−SCLL) has only to be met if the device does not stretch the low period [tw(SCLL)] of the SCL signal.

# Cb = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.

Stop

Start

Repeated

Start

Stop

SDA

SCL

Figure 4−38. I2C Receive Timings

TMS320DM641 Datasheet(PDF) 131 Page - Texas Instruments

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