HT48E10 datasheet(13/42 Pages) HOLTEK

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HT48E10

Rev. 1.50

October 31, 2006

Bit No.

Label

Function

0~2

PSC0~PSC2

Defines the prescaler stages, PSC2, PSC1, PSC0=

000: fINT=fSYS/2

001: fINT=fSYS/4

010: fINT=fSYS/8

011: fINT=fSYS/16

100: fINT=fSYS/32

101: fINT=fSYS/64

110: fINT=fSYS/128

111: fINT=fSYS/256

3TE

Defines the TMR active edge of the timer/event counter:

In Event Counter Mode (TM1,TM0)=(0,1):

1:count on falling edge;

0:count on rising edge

In Pulse Width measurement mode (TM1,TM0)=(1,1):

1: start counting on the rising edge, stop on the falling edge;

0: start counting on the falling edge, stop on the rising edge

TON

Enable or disable timer 0 counting (0=disable; 1=enable)

Unused bit, read as

²0²

TM0

TM1

Defines the operating mode

01=Event count mode (external clock)

10=Timer mode (internal clock)

11=Pulse width measurement mode

00=Unused

TMRC (0EH) Register

T M 1

T M 0

T M R

T E

T M 1

T M 0

T O N

P u l s e W i d t h

M e a s u r e m e n t

M o d e C o n t r o l

T i m e r / E v e n t C o u n t e r

P r e l o a d R e g i s t e r

T i m e r / E v e n t

C o u n t e r

D a t a B u s

R e l o a d

O v e r f l o w

t o I n t e r r u p t

1 / 2

B Z

8 - s t a g e P r e s c a l e r

8 - 1 M U X

f S Y S

f I N T

P S C 2 ~ P S C 0

( 1 / 2 ~ 1 / 2 5 6 )

Timer/Event Counter

measurement can be done. Until setting the TON, the

cycle measurement will function again as long as it re-

ceives further transient pulse. Note that, in this operat-

ing mode, the timer/event counter starts counting not

according to the logic level but according to the transient

edges. In the case of counter overflows, the counter is

reloaded from the timer/event counter preload register

and issues the interrupt request just like the other two

modes. To enable the counting operation, the timer ON

bit (TON; bit 4 of the TMRC) should be set to 1. In the

pulse width measurement mode, the TON will be

cleared automatically after the measurement cycle is

completed. But in the other two modes the TON can only

be reset by instructions. The overflow of the timer/event

counter is one of the wake-up sources. No matter what

the operation mode is, writing a

²0² to ETI can disable

the corresponding interrupt services.

In the case of timer/event counter OFF condition, writing

data to the timer/event counter preload register will also

reload that data to the timer/event counter. But if the

timer/event counter is turned on, data written to it will

only be kept in the timer/event counter preload register.

The timer/event counter will still operate until overflow

occurs. When the timer/event counter (reading TMR) is

read, the clock will be blocked to avoid errors. As clock

blocking may result in a counting error, this must be

taken into consideration by the programmer.

Bit0~bit2 of the TMRC can be used to define the

pre-scaling stages of the internal clock sources of the

timer/event counter. The definitions are as shown. The

overflow signal of the timer/event counter can be used

to generate PFD signals for buzzer driving.

HT48E10 Datasheet(PDF) 13 Page - Holtek Semiconductor Inc

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