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M27W800 Datasheet(PDF) 2 Page - STMicroelectronics

Part # M27W800
Description  8 Mbit 1Mb x 8 or 512Kb x 16 Low Voltage UV EPROM and OTP EPROM
PDF  15 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

M27W800 Datasheet(HTML) 2 Page - STMicroelectronics

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M27W800
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Figure 2B. LCC Connections
AI03603
A14
Q7
23
Q0
Q8
Q1
A4
A0
E
VSS
A3
A2
12
A16
1
BYTEVPP
A13
Q6
44
M27W800
A12
VSS
Q14
34
A1
A15
Q15A–1
G
Figure 2A. DIP Connections
G
Q0
Q8
A3
A0
E
VSS
A2
A1
A13
VSS
A14
A15
Q7
A12
A16
BYTEVPP
Q15A-1
Q5
Q2
Q3
VCC
Q11
Q4
Q14
A9
A8
A17
A4
A18
NC
A7
AI03602
M27W800
8
1
2
3
4
5
6
7
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
20
19
18
17
Q1
Q9
A6
A5
Q6
Q13
42
39
38
37
36
35
34
33
A11
A10
Q10
21
Q12
40
41
Table 1. Signal Names
A0-A18
Address Inputs
Q0-Q7
Data Outputs
Q8-Q14
Data Outputs
Q15A–1
Data Output / Address Input
E
Chip Enable
G
Output Enable
BYTEVPP
Byte Mode / Program Supply
VCC
Supply Voltage
VSS
Ground
NC
Not Connected Internally
DEVICE OPERATION
The operating modes of the M27W800 are listed in
the Operating Modes Table. A single power supply
is required in the read mode. All inputs are TTL
compatible except for VPP and 12V on A9 for the
Electronic Signature.
Read Mode
The M27W800 has two organisations, Word-wide
and Byte-wide. The organisation is selected by the
signal level on the BYTEVPP pin. When BYTEVPP
is at VIH the Word-wide organisation is selected
and the Q15A–1 pin is used for Q15 Data Output.
When the BYTEVPP pin is at VIL the Byte-wide or-
ganisation is selected and the Q15A–1 pin is used
for the Address Input A–1. When the memory is
logically regarded as 16 bit wide, but read in the
Byte-wide organisation, then with A–1 at VIL the
lower 8 bits of the 16 bit data are selected and with
A–1 at VIH the upper 8 bits of the 16 bit data are
selected.
The M27W800 has two control functions, both of
which must be logically active in order to obtain
data at the outputs. In addition the Word-wide or
Byte-wide organisation must be selected.
Chip Enable (E) is the power control and should be
used for device selection. Output Enable (G) is the
output control and should be used to gate data to
the output pins independent of device selection.
Assuming that the addresses are stable, the ad-
dress access time (tAVQV) is equal to the delay
from E to output (tELQV). Data is available at the
output after a delay of tGLQV from the falling edge
of G, assuming that E has been low and the ad-
dresses have been stable for at least tAVQV-tGLQV.



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