Notes:

1. Recommend transistion time for TXCLK In is 1.0 to 6.0 ns (figure 6).

2. Guaranteed by characterization.

3. Channel to channel skew is defined as the difference between TPPOS max limit and TPPOS minimum limit.

4. Guaranteed by design.

SYMBOL

PARAMETER

MIN

MAX

UNIT

LVDS Low-to-High Transition Time (Figure 5)

1.5

ns

LVDS High-to-Low Transition Time (Figure 5)

1.5

ns

Transmitter Output Pulse Position for Bit 0 (Figure 13)

-0.18

0.270

ns

Transmitter Output Pulse Position for Bit 1(Figure 13)

1.72

2.17

ns

Transmitter Output Pulse Position for Bit 2 (Figure 13)

3.63

4.08

ns

Transmitter Output Pulse Position for Bit 3 (Figure 13)

5.53

5.98

ns

Transmitter Output Pulse Position for Bit 4 (Figure 13)

7.44

7.89

ns

Transmitter Output Pulse Position for Bit 5 (Figure 13)

9.34

9.79

ns

Transmitter Output Pulse Position for Bit 6 (Figure 13)

11.25

11.70

ns

Channel to Channel skew (Figure 7)

0.45

ns

TCIP

TxCLK IN Period (Figure 8)

13.3

66.7

ns

TxCLK IN High Time (Figure 8)

0.35Tcip

0.65Tcip

ns

TxCLK IN Low Time (Figure 8)

0.35Tcip

0.65Tcip

ns

TxIN Setup to TxCLK IN (Figure 8)

1.0

0.5

ns

TxIN Hold to TxCLK IN (Figure 8)

0.7

0.5

ns

TCCD

TxCLK IN to TxCLK OUT Delay (Figure 9)

0.5

2.5

ns

TPLLS

Transmitter Phase Lock Loop Set (Figure 10)

10

ms

TPDD

Transmitter Powerdown Delay (Figure 12)

100

ns

f=75MHz

f=75MHz

f=75MHz

f=75MHz

f=75MHz

f=75MHz

f=75MHz

15MHz

75MHz

15MHz

75MHz