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UT54LVDS217 Datasheet(PDF) 1 Page - Aeroflex Circuit Technology |
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UT54LVDS217 Datasheet(HTML) 1 Page - Aeroflex Circuit Technology |
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1 / 14 page  1 FEATURES 15 to 75 MHz shift clock support Low power consumption Power-down mode <216 μW (max) Cold sparing all pins Narrow bus reduces cable size and cost Up to 1.575 Gbps throughput Up to 197 Megabytes/sec bandwidth 325 mV (typ) swing LVDS devices for low EMI PLL requires no external components Rising edge strobe Radiation-hardened design; total dose irradiation testing to MIL-STD-883 Method 1019 - Total-dose: 300 krad(Si) and 1 Mrad(Si) - Latchup immune (LET > 100 MeV-cm2/mg) Packaging options: - 48-lead flatpack Standard Microcircuit Drawing 5962-01534 - QML Q and V compliant part INTRODUCTION The UT54LVDS217 Serializer converts 21 bits of CMOS/TTL data into three LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fourth LVDS link. Every cycle of the transmit clock 21 bits of input data are sampled and transmitted. At a transmit clock frequency of 75MHz, 21 bits of TTL data are transmitted at a rate of 525 Mbps per LVDS data channel. Using a 75MHz clock, the data throughput is 1.575 Gbit/s (197 Mbytes/sec). The UT54LVDS217 Serializer allows the use of wide, high speed TTL interfaces while reducing overall EMI and cable size. All pins have Cold Spare buffers. These buffers will be high impedance when VDD is tied to VSS. Standard Products UT54LVDS217 Serializer Data Sheet May 8, 2007 PLL POWER DOWN TRANSMIT CLOCK IN CMOS/TTL INPUTS 21 DATA (LVDS) CLOCK (LVDS) Figure 1. UT54LVDS217 Serializer Block Diagram |
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