RX66N datasheet(22/175 Pages) RENESAS

22 / 175 page

RX66N Group

1. Overview

R01DS0344EJ0120 Rev.1.20

Page 22 of 175

Nov 15, 2023

Ethernet controller

REF50CK0

Input

50-MHz reference clock. This pin inputs a reference signal for

transmission/reception timing in RMII mode.

RMII0_CRS_DV

Input

This pin indicates that there are carrier detection signals and

valid receive data on RMII0_RXD1 and RMII0_RXD0 in RMII

mode.

RMII0_TXD0, RMII0_TXD1

Output

2-bit transmit data in RMII mode

RMII0_RXD0, RMII0_RXD1

Input

2-bit receive data in RMII mode

RMII0_TXD_EN

Output

Output pin for a data transmit enable signal in RMII mode

RMII0_RX_ER

Input

This pin indicates an error has occurred during reception of data

in RMII mode.

ET0_CRS

Input

Carrier detection/data reception enable pin

ET0_RX_DV

Input

This pin indicates that there are valid receive data on

ET0_ERXD3 to ET0_ERXD0.

ET0_EXOUT

Output

General-purpose external output pin

ET0_LINKSTA

Input

Input link status from the PHY-LSI.

ET0_ETXD0 to ET0_ETXD3

Output

4 bits of MII transmit data

ET0_ERXD0 to ET0_ERXD3

Input

4 bits of MII receive data

ET0_TX_EN

Output

Transmit enable pin. This pin functions as a signal indicating

that transmit data are ready on ET0_ETXD3 to ET0_ETXD0.

ET0_TX_ER

Output

Transmit error pin. This pin functions as a signal notifying the

PHY-LSI of an error during transmission.

ET0_RX_ER

Input

Receive error pin. This pin functions as a signal to recognize an

error during reception.

ET0_TX_CLK

Input

Transmit clock pin. This pin inputs a reference signal for output

timing from ET0_TX_EN, ET0_ETXD3 to ET0_ETXD0, and

ET0_TX_ER.

ET0_RX_CLK

Input

Receive clock pin. This pin inputs a reference signal for input

timing to ET0_RX_DV, ET0_ERXD3 to ET0_ERXD0, and

ET0_RX_ER.

ET0_COL

Input

Input collision detection signal.

ET0_WOL

Output

Receive Magic packet.

ET0_MDC

Output

Output reference clock signal for information transfer via

ET0_MDIO.

ET0_MDIO

I/O

Input or output bidirectional signal for exchange of management

information between this MCU and the PHY-LSI.

CLKOUT25M

Output

25-MHz clock output pin for PHY clock input

PHY management

interface

PMGI0_MDC

Output

Reference clock signal for information transfer by PMGI0_MDIO

PMGI0_MDIO

I/O

Bi-directional signal for the exchange of management

information between the PHY LSI chip and this MCU

USB 2.0 host/function

module

VCC_USB

Input

Power supply pin

VSS_USB

Input

Ground pin

USB0_DP

I/O

Input or output USB transceiver D+ data.

USB0_DM

I/O

Input or output USB transceiver D- data.

USB0_EXICEN

Output

Connect to the OTG power IC.

USB0_ID

Input

Connect to the OTG power IC.

USB0_VBUSEN

Output

USB VBUS power enable pin

USB0_OVRCURA/

USB0_OVRCURB

Input

USB overcurrent pins

USB0_VBUS

Input

USB cable connection/disconnection detection input pin

Table 1.4

Pin Functions (5/8)

Classifications

Pin Name

I/O

Description

RX66N Datasheet(PDF) 22 Page - Renesas Technology Corp

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