TMS320VC549 datasheet(10/64 Pages) TI

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TMS320VC549

FIXEDPOINT DIGITAL SIGNAL PROCESSOR

SPRS078G − SEPTEMBER 1998 − REVISED OCTOBER 2004

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

Signal Descriptions (Continued)

TERMINAL

DESCRIPTION

NAME

DESCRIPTION

TYPE†

SERIAL PORT 0 AND SERIAL PORT 1 SIGNALS (CONTINUED)

DX0

DX1

O/Z

Serial port transmit output. Serial data is transmitted from the XSR via DX. DX0 and DX1 are placed in the

high-impedance state when not transmitting and when EMU1/OFF is low.

FSR0

FSR1

Frame synchronization pulse for receive input. The falling edge of the FSR pulse initiates the data-receive

process, beginning the clocking of the RSR.

FSX0

FSX1

I/O/Z

Frame synchronization pulse for transmit input/output. The falling edge of the FSX pulse initiates the data transmit

process, beginning the clocking of the XSR. Following reset, the default operating condition of FSX is an input.

FSX0 and FSX1 can be selected by software to be an output when TXM in the serial control register is set to 1.

This pin goes into the high-impedance state when EMU1/OFF is low.

TDM SERIAL PORT SIGNALS

TCLKR

TDM receive clock input

TDR

TDM serial data-receive input

TFSR/TADD

I/O

TDM receive frame synchronization or TDM address

TCLKX

I/O/Z

TDM transmit clock

TDX

O/Z

TDM serial data-transmit output

TFSX/TFRM

I/O/Z

TDM transmit frame synchronization

HOST PORT INTERFACE SIGNALS

HD0−HD7

I/O/Z

Parallel bidirectional data bus. HD0−HD7 are placed in the high-impedance state when not outputting data. The

signals go into the high-impedance state when EMU1/OFF is low. These pins each have bus holders similar to

those on the address/data bus, but which are always enabled.

HCNTL0

HCNTL1

Control inputs

HBIL

Byte-identification input

HCS

Chip-select input

HDS1

HDS2

Data strobe inputs

HAS

Address strobe input

HR/W

Read/write input

HRDY

O/Z

Ready output. This signal goes into the high-impedance state when EMU1/OFF is low.

HINT

O/Z

Interrupt output. When the DSP is in reset, this signal is driven high

. The signal goes into the high-impedance

state when EMU1/OFF is low.

HPIENA

HPI module select input. This signal must be tied to a logic 1 state to have HPI selected. If this input is left open

or connected to ground, the HPI module will not be selected, internal pullup for the HPI input pins are enabled,

and the HPI data bus has keepers set. This input is provided with an internal pull-down resistor which is active

only when RS is low. HPIENA is sampled when RS goes high and ignored until RS goes low again. Refer to the

Electrical Characteristics section for the input current requirements for this pin.

SUPPLY PINS

CVDD

Supply

+VDD. CVDD is the dedicated power supply for the core CPU.

DVDD

Supply

+VDD. DVDD is the dedicated power supply for I/O pins.

VSS

Supply

Ground. VSS is the dedicated power ground for the device.

† I = Input, O = Output, Z = High impedance

TMS320VC549 Datasheet(PDF) 10 Page - Texas Instruments

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