M48T212A datasheet(10/20 Pages) STMICROELECTRONICS

10 / 20 page

M48T212A

10/20

Table 12. Alarm Repeat Modes

RPT5

RPT4

RPT3

RPT2

RPT1

Alarm Setting

1111

Once per Second

1110

Once per Minute

1100

Once per Hour

1000

Once per Day

0000

Once per Month

0000

Once per Year

WRITE MODE

The M48T212A is in the Write Mode whenever W

(Write Enable) and E (Chip Enable) are in a low

state after the address inputs are stable. The start

of a write is referenced from the latter occurring

falling edge of W or E. A write is terminated by the

earlier rising edge of W or E. The addresses must

be held valid throughout the cycle. E or W must re-

turn high for a minimum of tEHAX from Chip Enable

or tWHAX from Write Enable prior to the initiation of

another read or write cycle. Data-in must be valid

tDVWH prior to the end of write and remain valid for

tWHDX afterward.

G should be kept high during write cycles to avoid

bus contention; although, if the output bus has

been activated by a low on E and G a low on W will

disable the outputs tWLQZ after W falls.

When E is low during the write, one of the on-

board TIMEKEEPER registers will be selected and

data will be written into the device. When EX is low

(and E is high) an external SRAM location is se-

lected.

Note: Care should be taken to avoid taking both E

and EX low simultaneously to avoid bus conten-

tion.

DATA RETENTION MODE

With valid VCC applied, the M48T212A can be ac-

cessed as described above with read or write cy-

cles. Should the supply voltage decay, the

M48T212A will automatically deselect, write pro-

tecting itself (and any external SRAM) when VCC

falls between VPFD (max) and VPFD (min). This is

accomplished by internally inhibiting access to the

clock registers via the E signal. At this time, the

Reset pin (RST) is driven active and will remain

active until VCC returns to nominal levels.

External RAM access is inhibited in a similar man-

ner by forcing E1CON and E2CON to a high level.

This level is within 0.2V of the VBAT. E1CON and

E2CON will remain at this level as long as VCC re-

mains at an out-of tolerance condition.

When VCC falls below the level of the battery

(VBAT), power input is switched from the VCC pin

to the battery and the clock registers and external

SRAM are maintained from the attached battery

supply. All outputs become high impedance. The

VOUT pin is capable of supplying 100µA of current

to the attached memory with less than 0.3V drop

under this condition. On power up, when VCC re-

turns to a nominal value, write protection contin-

ues for 200ms (max) by inhibiting E1CON or

E2CON.

Figure 9. Alarm Interrupt Reset Waveforms

AI03021

A0-A3

ACTIVE FLAG BIT

ADDRESS 0h

IRQ/FT

HIGH-Z

M48T212A Datasheet(PDF) 10 Page - STMicroelectronics

M48T212A Datasheet(HTML) 10 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

Datasheet Download

Link URL