M48T201VMH datasheet(7/33 Pages) STMICROELECTRONICS

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M48T201Y, M48T201V

OPERATION

Automatic backup and write protection for an ex-

ternal SRAM is provided through VOUT, ECON, and

GCON pins. (Users are urged to insure that voltage

specifications, for both the SUPERVISOR chip

and external SRAM chosen, are similar.) The

SNAPHAT® containing the lithium energy source

is used to retain the RTC and RAM data in the ab-

sence of VCC power through the VOUT pin. The

chip enable output to RAM (ECON) and the output

enable output to RAM (GCON) are controlled dur-

ing power transients to prevent data corruption.

The date is automatically adjusted for months with

less than 31 days and corrects for leap years (valid

until 2100). The internal watchdog timer provides

programmable alarm windows.

The nine clock bytes (7FFFFh-7FFF9h and

7FFF1h) are not the actual clock counters, they

are memory locations consisting of BiPORT™

READ/WRITE memory cells within the static RAM

array. Clock circuitry updates the clock bytes with

current information once per second. The informa-

tion can be accessed by the user in the same man-

ner as any other location in the static memory

array. Byte 7FFF8h is the clock control register.

This byte controls user access to the clock infor-

mation and also stores the clock calibration set-

ting.

Byte 7FFF7h contains the watchdog timer setting.

The watchdog timer can generate either a reset or

an interrupt, depending on the state of the Watch-

dog Steering Bit (WDS). Bytes 7FFF6h-7FFF2h

include bits that, when programmed, provide for

clock alarm functionality. Alarms are activated

when the register content matches the month,

date, hours, minutes, and seconds of the clock

registers. Byte 7FFF1h contains century informa-

tion. Byte 7FFF0h contains additional flag informa-

tion pertaining to the watchdog timer, the alarm

condition, the battery status and square wave out-

put operation. 4 bits are included within this regis-

ter (RS0-RS3) that are used to program the

Square Wave Output Frequency (see Table

7., page 18). The M48T201Y/V also has its own

Power-Fail Detect circuit. This control circuitry

constantly monitors the supply voltage for an out

of tolerance condition. When VCC is out of toler-

ance, the circuit write protects the TIMEKEEPER®

security in the midst of unpredictable system oper-

ation. As VCC falls below the Battery Back-up

Switchover Voltage (VSO), the control circuitry au-

tomatically switches to the battery, maintaining

data and clock operation until valid power is re-

stored.

Address Decoding

The M48T201Y/V accommodates 19 address

lines (A0-A18) which allow direct connection of up

to 512K bytes of static RAM. Regardless of SRAM

density used, timekeeping, watchdog, alarm, cen-

tury, flag, and control registers are located in the

upper RAM locations. All TIMEKEEPER registers

reside in the upper RAM locations without conflict

by inhibiting the GCON (output enable RAM) signal

during clock access. The RAM's physical locations

are transparent to the user and the memory map

looks continuous from the first clock address to the

upper most attached RAM addresses.

Table 2. Operating Modes

Note: X = VIH or VIL; VSO = Battery Back-up Switchover Voltage

1. See Table 14., page 27 for details.

Mode

VCC

DQ7-DQ0

Power

Deselect

4.5V to 5.5V

3.0V to 3.6V

VIH

High-Z

Standby

WRITE

VIL

DIN

Active

READ

VIL

VIH

DOUT

Active

READ

VIL

VIH

High-Z

Active

Deselect

VSO to VPFD (min)

(1)

High-Z

CMOS Standby

Deselect

≤ VSO(1)

High-Z

Battery Back-Up

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