M48T201VMH datasheet(8/33 Pages) STMICROELECTRONICS

8 / 33 page

M48T201Y, M48T201V

8/33

READ Mode

The M48T201Y/V executes a READ Cycle when-

ever W (WRITE Enable) is high and E (Chip En-

able) is low. The unique address specified by the

address inputs (A0-A18) defines which one of the

on-chip TIMEKEEPER® registers or external

SRAM locations is to be accessed. When the ad-

dress presented to the M48T201Y/V is in the

range of 7FFFFh-7FFF0h, one of the on-board

TIMEKEEPER registers is accessed and valid

data will be available to the eight data output driv-

ers within tAVQV after the address input signal is

stable, providing that the E and G access times

are also satisfied. If they are not, then data access

must be measured from the latter occurring signal

(E or G) and the limiting parameter is either tELQV

for E or tGLQV for G rather than the address access

time. When one of the on-chip TIMEKEEPER reg-

isters is selected for READ, the GCON signal will

remain inactive throughout the READ Cycle.

When

the

address value

presented to the

M48T201Y/V is outside the range of TIMEKEEP-

ER registers, an external SRAM location will be

selected. In this case the G signal will be passed

to the GCON pin, with the specified delay times of

tAOEL or tOERL.

Figure 5. GCON Timing When Switching Between RTC and External SRAM

AI02333

GCON

tAOEL

ADDRESS

00000h - 7FFEFh

7FFF0h - 7FFFFh

00000h - 7FFEFh

7FFF0h - 7FFFFh

tAOEH

tOERL

tRO

External SRAM

RTC

External SRAM

RTC

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