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PRELIMINARY DATA

May 2002

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

M50FW002

2 Mbit (256Kb x8, Boot Block)

3V Supply Firmware Hub Flash Memory

FEATURES SUMMARY

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SUPPLY VOLTAGE

Read Operations

(optional)

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TWO INTERFACES

– Firmware Hub (FWH) Interface for embedded

operation with PC Chipsets

– Address/Address Multiplexed (A/A Mux)

Interface for programming equipment

compatibility

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FIRMWARE HUB (FWH) HARDWARE

INTERFACE MODE

– 5 Signal Communication Interface supporting

Read and Write Operations

– Hardware Write Protect Pins for Block

Protection

– Register Based Read and Write Protection

– 5 Additional General Purpose Inputs for

platform design flexibility

– Synchronized with 33MHz PCI clock

– Multi-byte Read Operation (1-byte, 16-byte,

32-byte)

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PROGRAMMING TIME

– 10 µs typical

– Quadruple Byte Programming Option

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7

MEMORY BLOCKS

– 1 Boot Block (Top Location)

– 4 Main Blocks and 2 Parameter Blocks

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PROGRAM/ERASE CONTROLLER

– Embedded Byte Program, Block Erase and

Chip Erase algorithms

– Status Register Bits

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PROGRAM and ERASE SUSPEND

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FOR USE in PC BIOS APPLICATIONS

Figure 1. Packages

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ELECTRONIC SIGNATURE

– Manufacturer Code: 20h

– Device Code: 29h

PLCC32 (K)