R31DS0128EU0117 Rev.1.17

Page 20

May 8, 2026

RC32312, RC32308 Datasheet

2.22

SPI Target Timing Diagrams

Figure 5. SPI Target Timing Diagrams

2.23

SPI Target Timing Characteristics

Table 23. SPI Target Timing Characteristics

Symbol

Parameter

Minimum

Typical

Maximum

Unit

fMAX

Maximum operating frequency

0.1

-

20

MHz

tPWH

SCLK pulse width high

14

-

-

ns

tPWL

SCLK pulse width low

14

-

-

ns

tSU1

nCS setup time to SCLK rising or falling edge

10

-

-

ns

tHD1

nCS hold time from SCLK rising or falling edge

2

-

-

ns

tSU2

SDIO setup time to SCLK rising or falling edge

4

-

-

ns

tHD2

SDIO hold time from SCLK rising or falling edge

3

-

-

ns

tD1

Read data valid time from SCLK rising or falling edge

4.7

-

7.4

ns

tD2

SDIO read data Hi-Z time from CS high [1]

1. This is the time until the device releases the signal. Rise time to any specific voltage is dependent on pull-up resistor strength and PCB trace

loading.

0

-

14.5

ns

nCS

SCLK

SDI

SDIO (spi_del_out = 0)

Hi-Z

Hi-Z

spi_clk_sel = 0

nCS

SCLK

SDI

R/W

A(n)

A(n-1)

R/W

A(n)

A(n-1)

Write D(n)

Write D(n)

Hi-Z

Read D(n)

Read D(n)

Hi-Z

Hi-Z

Hi-Z

Hi-Z

Read D(n)

Read D(n)

A(0)

SDIO (spi_del_out = 1)

Write D(n-1)

spi_clk_sel = 1

SDIO (spi_del_out = 0)

SDIO (spi_del_out = 1)

A(0)

Write D(n-1)

Read D(0)

Read D(0)

Write D(0)

Read D(0)

Read D(0)

Wr D(0)