DEVICE INFORMATION

TPS53124

TERMINAL FUNCTIONS

TERMINAL

I/O

DESCRIPTION

NAME

GFN24

TSSOP28

Supply input for high-side NFET driver (boost terminal). Connect

VBST1,

capacitor from this pin to respective LL terminals. An internal PN diode is

23, 8

1, 14

I

VBST2

connected between VREG5 to each of these pins. User can add external

schottky diode if forward drop is critical to drive the NFET.

EN1, EN2

24, 7

3, 12

I

Channel 1 and Channel 2 enable pins.

Output connections to SMPS. These terminals serve ON-time adjustment,

VO1, VO2

1, 6

4, 11

I

output discharge.

VFB1, VFB2

2, 5

5, 10

I

SMPS feedback inputs. Connect with feedback resistor divider.

GND

3

7

I

Signal ground pin.

High-side NFET driver outputs. LL referenced floating drivers. The gate

DRVH1,

22, 9

28, 15

O

drive voltage is defined by the voltage across VBST to LL node flying

DRVH2

capacitor.

Switch-node connections for high-side drivers. Also serve as input to

LL1, LL2

21, 10

27, 16

I/O

current comparators.

DRVL1,

Synchronous NFET driver outputs. PGND referenced drivers. The gate

20, 11

26, 17

O

DRVL2

drive voltage is defined by VREG5 voltage.

Ground returns for DRVL1 and DRVL2. Also serve as input of current

PGND1,

19, 12

25, 18

I/O

comparators. Connect PGND1, PGND2 and GND strongly together near

PGND2

the device.

Over-current trip point set input. Connect resistor from this pin to GND to

TRIP1,

18, 13

24, 19

I

TRIP2

GND is compared to voltage across PGND and LL at over current

comparator.

VIN

17

23

I

Supply Input for 5-V linear regulator.

5-V supply input for the entire control circuit except the NFET drivers.

V5FILT

15

21

I

Connect capacitor (typical 1

µF) from GND to V5FILT. V5FILT is

connected to VREG5 via internal resistor.

5-V power supply output. VREG5 is connected to V5FILT via internal

VREG5

16

20

O

resistor.

TEST1,

4, 14

8, 20

I/O

Used for test only. Pin should be connected to GND

TEST2

6

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Product Folder Link(s): TPS53124