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ICS854054 Datasheet(PDF) 10 Page - Integrated Circuit Systems

Part # ICS854054
Description  DIFFERENTIAL-TO-LVDS CLOCK MULTIPLEXER
PDF  13 Pages
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Manufacturer  ICST [Integrated Circuit Systems]
Direct Link  http://www.icst.com
Logo ICST - Integrated Circuit Systems

ICS854054 Datasheet(HTML) 10 Page - Integrated Circuit Systems

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854054AG
www.icst.com/products/hiperclocks.html
REV. A MARCH 29, 2006
10
Integrated
Circuit
Systems, Inc.
ICS854054
4:1
DIFFERENTIAL-TO-LVDS CLOCK MULTIPLEXER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS854054.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS854054 is the sum of the core power.
The following is the power dissipation for V
DD = 3.3V + 5% = 3.465V, which gives worst case results.
• Power (core)
MAX = VDD_MAX * IDD_MAX = 3.465V * 90mA = 311.85mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of
the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj =
θ
JA * Pd_total + TA
Tj = Junction Temperature
q
JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T
A = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance
θ
JA must be used.
Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 81.8°C/W per
Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.312W * 81.8°C/W = 110.5°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air
flow, and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE
θθθθθ
JA
FOR
16-LEAD TSSOP, FORCED CONVECTION
θθθθθ
JA by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
137.1°C/W
118.2°C/W
106.8°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
89.0°C/W
81.8°C/W
78.1°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.



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