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STM32F103X8 Datasheet(PDF) 64 Page - STMicroelectronics

Part # STM32F103X8
Description  Performance line, ARM-based 32-bit MCU with Flash, USB, CAN, seven 16-bit timers, two ADCs and nine communication interfaces
PDF  84 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32F103X8 Datasheet(HTML) 64 Page - STMicroelectronics

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Electrical characteristics
STM32F103xx
64/84
5.3.17
12-bit ADC characteristics
Unless otherwise specified, the parameters given in Table 44 are derived from tests
performed under ambient temperature, fPCLK2 frequency and VDDA supply voltage
conditions summarized in Table 7.
Note:
It is recommended to perform a calibration after each power-up.
Table 44.
ADC characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VDDA
ADC power supply
2.4
3.6
V
VREF+
Positive reference voltage
2.4
VDDA
V
IVREF
Current on the VREF input pin
160(1)
220(1)
µA
fADC
ADC clock frequency
0.6
14
MHz
fS
(2)
Sampling rate
0.05
1
MHz
fTRIG
(2)
External trigger frequency
fADC = 14 MHz
823
kHz
17
1/fADC
VAIN
Conversion voltage range(3)
0 (VSSA or VREF-
tied to ground)
VREF+
V
RAIN
(2)
External input impedance
See Equation 1 and Table 45
k
Ω
RADC
(2)
Sampling switch resistance
1
k
Ω
CADC
(2)
Internal sample and hold
capacitor
5pF
tCAL
(2)
Calibration time
fADC = 14 MHz
5.9
µs
83
1/fADC
tlat
(2)
Injection trigger conversion
latency
fADC = 14 MHz
0.214
µs
3(4)
1/fADC
tlatr
(2)
Regular trigger conversion
latency
fADC = 14 MHz
0.143
µs
2(4)
1/fADC
tS
(2)
Sampling time
fADC = 14 MHz
0.107
17.1
µs
1.5
239.5
1/fADC
tSTAB
(2)
Power-up time
0
0
1
µs
tCONV
(2)
Total conversion time
(including sampling time)
fADC = 14 MHz
118
µs
14 to 252 (tS for sampling +12.5 for
successive approximation)
1/fADC
1.
Data based on characterization results, not tested in production.
2.
Guaranteed by design, not tested in production.
3.
VREF+ can be internally connected to VDDA and VREF- can be internally connected to VSSA, depending on the package.
Refer to Section 3: Pin descriptions for further details.
4.
For external triggers, a delay of 1/fPCLK2 must be added to the latency specified in Table 44.



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