SED1565DBB datasheet(21/54 Pages) EPSON

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S1D15300 Series

Rev.1.4

EPSON

5–9

Chip Select Inputs

The S1D15300 series has two chip select pins, CS1 and CS2 and can

interface to a microprocessor when CS1 is low and CS2 is high.

When these pins are set to any other combination, D0 to D7 are high

impedance and A0, RD and WR inputs are disabled.

When serial input interface is selected, the shift register and counter

are reset.

Access to Display Data RAM and Internal Registers

The S1D15300 series can perform a series of pipeline processing

between LSI’s using bus holder of internal data bus in order to match

the operating frequency of display RAM and internal registers with

the microprocessor. For example, the microprocessor reads data

from display RAM in the first read (dummy) cycle, stores it in bus

holder, and outputs it onto system bus in the next data read cycle.

Also, the microprocessor temporarily stores display data in bus

holder, and stores it in display RAM until the next data write cycle

starts.

When viewed from the microprocessor, the S1D15300 series access

speed greatly depends on the cycle time rather than access time to the

display RAM (

tACC). It shows the data transfer speed to/from the

microprocessor can increase. If the cycle time is inappropriate, the

microprocessor can insert the NOP instruction that is equivalent to

the wait cycle setup. However, there is a restriction in the display

RAM read sequence. When an address is set, the specified address

data is NOT output at the immediately following read instruction.

The address data is output during second data read. A single dummy

read must be inserted after address setup and after write cycle (refer

to Figure 2).

•Write

•Read

Write signal

Bus holder

Internal

timing

DATA

MPU

n+1

n+2

n+3

Latched

n+1

n+2

n+3

Address

preset

Read signal

Column

address

Bus holder

Internal

timing

Preset

Incremented

Set address n

Dummy read

Data Read address n

Data Read address n+1

DATA

n+1

N+1

N+2

n+1

n+2

MPU

Figure 2

Busy Flag

The Busy flag is set when the S1D15300 series starts to operate.

During operating, it accepts Read Status instruction only. The busy

flag signal is output at pin D7 when Read Status is issued. If the cycle

time (

tcyc) is correct, the microprocessor needs not to check the flag

before issuing a command. This can greatly improve the microproc-

essor performance.

Initial Display Line Register

When the display RAM data is read, the display line according to

COM0 (usually, the top line of screen) is determined using register

data. The register is also used for screen scrolling and page

switching.

The Set Display Start Line command sets the 6-bit display start

address in this register. The register data is preset on the line counter

each time FR signal status changes. The line counter is incremented

by CL signal and it generates a line address to allow 132-bit

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