4

1138IS–FPSLI–1/08

AT94KAL Series FPSLIC Summary

The embedded AVR core achieves throughputs approaching 1 MIPS per MHz by executing

powerful instructions in a single-clock cycle, and allows system designers to optimize power

consumption versus processing speed. The AVR core is based on an enhanced RISC architec-

ture that combines a rich instruction set with 32 general-purpose working registers. All 32

registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent

registers to be accessed in one single instruction executed in one clock cycle. The resulting

architecture is more code-efficient while achieving throughputs up to ten times faster than con-

ventional CISC microcontrollers at the same clock frequency. The AVR executes out of on-chip

SRAM. Both the FPGA configuration SRAM and the AVR instruction code SRAM can be auto-

matically loaded at system power-up using Atmel’s In-System Programmable (ISP) AT17 Series

EEPROM Configuration Memories.

State-of-the-art FPSLIC design tools, System Designer, were developed in conjunction with the

FPSLIC architecture to help reduce overall time-to-market by integrating microcontroller devel-

opment and debug, FPGA development and Place and Route, and complete system

co-verification in one easy-to-use software tool.

Table 1-2.

FPSLIC Configuration Devices

FPSLIC Device

FPSLIC Configuration

Device

Configuration Data

Spare Memory

AT94K05

AT17LV256

226520 Bits

35624 Bits

AT94K10

AT17LV512

430488 Bits

93800 Bits

AT94K40

AT17LV010

815382 Bits

233194 Bits