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LAN9312 Datasheet(PDF) 102 Page - SMSC Corporation |
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LAN9312 Datasheet(HTML) 102 Page - SMSC Corporation |
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102 / 458 page  High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.2 (04-08-08) 102 SMSC LAN9312 DATASHEET RX Status FIFO 00 RX Status FIFO PEEK 00 TX Status FIFO 00 TX Status FIFO PEEK 00 ID_REV 00 IRQ_CFG 135 3 INT_STS 90 2 INT_EN 45 1 BYTE_TEST 00 FIFO_INT 45 1 RX_CFG 45 1 TX_CFG 45 1 HW_CFG 45 1 RX_DP_CTRL 45 1 RX_FIFO_INF 00 TX_FIFO_INF 135 3 PMT_CTRL 315 7 GPT_CFG 45 1 GPT_CNT 135 3 FREE_RUN 180 4 RX_DROP 00 MAC_CSR_CMD 45 1 MAC_CSR_DATA 45 1 AFC_CFG 45 1 1588_CLOCK_HI_RX_CAPTURE_1 00 1588_CLOCK_LO_RX_CAPTURE_1 00 1588_SEQ_ID_SRC_UUID_HI_RX_CAPTURE_1 00 1588_SRC_UUID_LO_RX_CAPTURE_1 00 1588_CLOCK_HI_TX_CAPTURE_1 00 1588_CLOCK_LO_TX_CAPTURE_1 00 1588_SEQ_ID_SRC_UUID_HI_TX_CAPTURE_1 00 Table 8.1 Read After Write Timing Rules (continued) REGISTER NAME MINIMUM WAIT TIME FOR READ FOLLOWING ANY WRITE CYCLE (IN NS) NUMBER OF BYTE_TEST READS (ASSUMING TCYC OF 45NS) |
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