LAN9312 datasheet(225/458 Pages) SMSC

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High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface

Datasheet

SMSC LAN9312

225

Revision 1.2 (04-08-08)

DATASHEET

Lock Enable GPIO 8 (LOCK_GPIO_8)

This bit enables/disables the GPIO 8 lock. This lock prevents a 1588 capture

from overwriting the Clock value if the 1588_GPIO8 interrupt in the 1588

Interrupt Status and Enable Register (1588_INT_STS_EN) is already set

due to a previous capture.

0: Disables GPIO 8 Lock

1: Enables GPIO 8 Lock

R/W

4:3

GPIO 9 Clock Event Mode (GPIO_EVENT_9)

These bits determine the output on GPIO 9 when a clock target compare

event occurs.

00: 100ns pulse output

01: Toggle output

10: 1588_TIMER_INT bit value in the 1588_INT_STS_EN register output

11: RESERVED

Note:

The 1588_GPIO_OE[9] bit in the General Purpose I/O

Configuration Register (GPIO_CFG) must be set in order for the

GPIO output to be controlled by the 1588 block.

Note:

The polarity of the pulse or level is set by the

GPIO_EVENT_POL_9 bit in the General Purpose I/O Configuration

GPIO buffer type.

R/W

00b

2:1

GPIO 8 Clock Event Mode (GPIO_EVENT_8)

These bits determine the output on GPIO 8 when a clock target compare

event occurs.

00: 100ns pulse output

01: Toggle output

10: 1588_TIMER_INT bit value in the 1588_INT_STS_EN register output

11: RESERVED

Note:

The 1588_GPIO_OE[8] bit in the General Purpose I/O

Configuration Register (GPIO_CFG) must be set in order for the

GPIO output to be controlled by the 1588 block.

Note:

The polarity of the pulse or level is set by the

GPIO_EVENT_POL_8 bit in the General Purpose I/O Configuration

GPIO buffer type.

R/W

00b

Reload/Add (RELOAD_ADD)

This bit determines the course of action when a clock target compare event

occurs. When set, the 1588 Clock Target High-DWORD Register

(1588_CLOCK_TARGET_HI) and 1588 Clock Target Low-DWORD Register

(1588_CLOCK_TARGET_LO) are loaded from the 1588 Clock Target

Reload High-DWORD Register (1588_CLOCK_TARGET_RELOAD_HI) and

1588 Clock Target Reload/Add Low-DWORD Register

(1588_CLOCK_TARGET_RELOAD_LO) when a clock target compare event

occurs. When low, the Clock Target Low and High Registers are

incremented by the Clock Target Reload Low Register when a clock target

compare event occurs.

0: Reload upon a clock target compare event

1: Increment upon a clock target compare event

R/W

BITS

DESCRIPTION

TYPE

DEFAULT

LAN9312 Datasheet(PDF) 225 Page - SMSC Corporation

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