LAN9312 datasheet(224/458 Pages) SMSC

224 / 458 page

High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface

Datasheet

Revision 1.2 (04-08-08)

224

SMSC LAN9312

DATASHEET

Alternate MAC Address 1 Enable Port 0(Host MAC)

(MAC_ALT1_EN_MII)

This bit enables/disables the alternate MAC address 1 on Port 0.

0: Disables alternate MAC address on Port 0

1: Enables MAC address 01:00:5E:00:01:82 as a PTP address on Port 0

R/W

Alternate MAC Address 2 Enable Port 0(Host MAC)

(MAC_ALT2_EN_MII)

This bit enables/disables the alternate MAC address 2 on Port 0.

0: Disables alternate MAC address on Port 0

1: Enables MAC address 01:00:5E:00:01:83 as a PTP address on Port 0

R/W

Alternate MAC Address 3 Enable Port 0(Host MAC)

(MAC_ALT3_EN_MII)

This bit enables/disables the alternate MAC address 3 on Port 0.

0: Disables alternate MAC address on Port 0

1: Enables MAC address 01:00:5E:00:01:84 as a PTP address on Port 0

R/W

User Defined MAC Address Enable Port 0(Host MAC)

(MAC_USER_EN_MII)

This bit enables/disables the auxiliary MAC address on Port 0. The auxiliary

address is defined via the 1588_AUX_MAC_HI and 1588_AUX_MAC_LO

registers.

0: Disables auxiliary MAC address on Port 0

1: Enables auxiliary MAC address as a PTP address on Port 0

R/W

Lock Enable RX Port 0(Host MAC) (LOCK_RX_MII)

This bit enables/disables the RX lock. This lock prevents a 1588 capture

from overwriting the Clock, UUDI and Sequence ID values if the 1588 RX

interrupt for Port 0 is ready set due to a previous capture.

0: Disables RX Port 0 Lock

1: Enables RX Port 0 Lock

Note:

For Port 0, receive is defined as data from the switch fabric, while

transmit is to the switch fabric.

R/W

Lock Enable TX Port 0(Host MAC) (LOCK_TX_MII)

This bit enables/disables the TX lock. This lock prevents a 1588 capture

from overwriting the Clock, UUDI and Sequence ID values if the 1588 TX

interrupt for Port 0 is ready set due to a previous capture.

0: Disables TX Port 0 Lock

1: Enables TX Port 0 Lock

Note:

For Port 0, receive is defined as data from the switch fabric, while

transmit is to the switch fabric.

R/W

RESERVED

Lock Enable GPIO 9 (LOCK_GPIO_9)

This bit enables/disables the GPIO 9 lock. This lock prevents a 1588 capture

from overwriting the Clock value if the 1588_GPIO9 interrupt in the 1588

Interrupt Status and Enable Register (1588_INT_STS_EN) is already set

due to a previous capture.

0: Disables GPIO 9 Lock

1: Enables GPIO 9 Lock

R/W

BITS

DESCRIPTION

TYPE

DEFAULT

LAN9312 Datasheet(PDF) 224 Page - SMSC Corporation

LAN9312 Datasheet(HTML) 224 Page - SMSC Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL