M58LW032A datasheet(14/61 Pages) STMICROELECTRONICS

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M58LW032A

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put Enable must remain High, VIH, during the

whole Asynchronous Bus Write operation. See

Figures 15 and 17 Asynchronous Latch Controlled

Write AC Waveforms, and Tables 18 and 19,

Asynchronous Write and Latch Controlled Write

AC Characteristics, for details of the timing re-

quirements.

Output Disable. The Data Inputs/Outputs are in

the high impedance state when the Output Enable

is High.

Standby. When Chip Enable is High, VIH, the

memory enters Standby mode and the Data In-

puts/Outputs pins are placed in the high imped-

ance state regardless of Output Enable or Write

Enable. The Supply Current is reduced to the

Standby Supply Current, IDD1.

During Program or Erase operations the memory

will continue to use the Program/Erase Supply

Current, IDD3, for Program or Erase operations un-

til the operation completes.

Automatic Low Power. If there is no change in

the state of the bus for a short period of time during

Asynchronous Bus Read operations the memory

enters Auto Low Power mode where the internal

Supply Current is reduced to the Auto-Standby

Supply Current, IDD5. The Data Inputs/Outputs will

still output data if a Bus Read operation is in

progress.

Automatic Low Power is only available in Asyn-

chronous Read modes.

Power-Down. The memory is in Power-Down

mode when Reset/Power-Down, RP, is Low. The

power consumption is reduced to the Power-Down

level, IDD2, and the outputs are high impedance,

independent of Chip Enable, Output Enable or

Write Enable.

Table 2. Asynchronous Bus Operations

Note: 1. X = Don’t Care VIL or VIH. High = VIH or VHH.

Bus Operation

Step

A1-A21

DQ0-DQ15

Asynchronous Bus Read

VIL

VIH

High

VIL

Address

Data Output

Asynchronous Latch

Controlled Bus Read

Address Latch

VIL

VIH

High

VIL

Address

High Z

Read

VIL

VIH

High

VIH

Data Output

Asynchronous Page Read

VIL

VIH

High

VIL

Address

Data Output

Asynchronous Bus Write

VIL

VIH

VIL

High

VIL

Address

Data Input

Asynchronous Latch

Controlled Bus Write

Address Latch

VIL

VIH

VIL

High

VIL

Address

Data Input

Output Disable

VIL

VIH

High

High Z

Standby

VIH

High

High Z

Power-Down

VIL

High Z

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