M59DR016CZB datasheet(6/37 Pages) STMICROELECTRONICS

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M59DR016C, M59DR016D

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Table 8. User Bus Operations (1)

Note: 1. X = Don’t care.

Table 9. Read Electronic Signature (AS and Read CFI instructions)

Table 10. Read Block Protection (AS and Read CFI instructions)

Table 11. Read Configuration Register (AS and Read CFI instructions)

Operation

DQ15-DQ0

Write

VIL

VIH

VIL

VIH

Data Input

Output Disable

VIL

VIH

Hi-Z

Standby

VIH

Hi-Z

Reset / Power Down

VIL

VIH

Hi-Z

Block Locking

VIL

VIH

VIL

Code

Device

A7-A2

Other

Addresses

DQ15-DQ8

DQ7-DQ0

Manufacturer Code

VIL

VIH

VIL

Don’t Care

00h

20h

Device Code

M59DR016C

VIL

VIH

VIL

Don’t Care

22h

93h

M59DR016D

VIL

VIH

VIL

Don’t Care

22h

94h

Block Status

A19-A12

A7-A2

Other

Addresses

DQ0

DQ1

DQ15-DQ2

Protected Block

VIL

VIH

VIL

VIH

Block Address

Don’t Care

0000h

Unprotected Block

VIL

VIH

VIL

VIH

Block Address

Don’t Care

0000h

Locked Block

VIL

VIH

VIL

VIH

Block Address

Don’t Care

0000h

RP Function

A7-A2

Other Addresses

DQ10

DQ9-DQ0

DQ15-DQ11

Reset

VIL

VIH

Don’t Care

Reset/Power Down

VIL

VIH

Don’t Care

Automatic Standby. When in Read mode, after

150ns of bus inactivity and when CMOS levels are

driving the addresses, the chip automatically en-

ters a pseudo-standby mode where consumption

is reduced to the CMOS standby value, while out-

puts still drive the bus.

Power Down. The memory is in Power Down

when the Configuration Register is set for Power

Down and RP is at VIL. The power consumption is

reduced to the Power Down level, and Outputs are

in high impedance, independent of the Chip En-

able E, Output Enable G or Write Enable W inputs.

Block Locking. Any combination of blocks can

be temporarily protected against Program or

Erase by setting the lock register and pulling WP

to VIL (see Block Lock instruction).

Dual Bank Operations. The Dual Bank allows to

read data from one bank of memory while a pro-

gram or erase operation is in progress in the other

bank of the memory. Read and Write cycles can

be initiated for simultaneous operations in different

banks without any delay. Status Register during

Program or Erase must be monitored using an ad-

dress within the bank being modified.

Output Disable. The data outputs are high im-

pedance when the Output Enable G is at VIH with

Write Enable W at VIH.

Standby. The memory is in standby when Chip

Enable E is at VIH and the P/E.C. is idle. The pow-

er consumption is reduced to the standby level

and the outputs are high impedance, independent

of the Output Enable G or Write Enable W inputs.

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