DIO6012B

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DIO6012B• Rev. 1.4

Output capacitor COUT

The output capacitor is selected to handle the output ripple noise requirements. Both steady state ripple and

transient requirements must be taken into consideration when selecting this capacitor. For the best

performance, it is recommended to use X5R or better grade ceramic capacitor with 6V rating and greater than

40µF capacitance.

Output inductor L:

There are several considerations in choosing this inductor.

1) Choose the inductance to provide the desired ripple current. It is suggested to choose the ripple current to

be about 40% of the maximum output current. The inductance is calculated as:

L=

%

40

)

/

1

(

,

,







MAX

OUT

SW

MAX

IN

OUT

OUT

I

F

V

V

V

where Fsw is the switching frequency and IOUT,MAX is the maximum load current. The DIO6012B regulator IC

is quite tolerant of different ripple current amplitude. Consequently, the final choice of inductance can be

slightly off the calculation value without significantly impacting the performance.

2) The saturation current rating of the inductor must be selected to be greater than the peak inductor current

under full load conditions.

ISAT,MIN>IOUT,MAX +

L

F

V

V

V

SW

MAX

IN

OUT

OUT







2

)

/

1

(

,

3) The DCR of the inductor and the core loss at the switching frequency must be low enough to achieve the

desired efficiency requirement. It is desirable to choose an inductor with DCR<50mΩ to achieve a good overall

efficiency.

Enable Operation

Pulling the EN pin low (<0.4V) will shut down the device. During shut down mode, the DIO6012B shutdown

current drops to lower than 0.1µA. Driving the EN pin high (>1.2V) will turn on the IC again.

Load Transient Considerations: The DIO6012B regulator IC integrates the compensation components to

achieve good stability and fast transient responses. In some applications, adding a 22pF ceramic cap in

parallel with R1 may further speed up the load transient responses and is thus recommended for applications

with large load transient step requirements.

Layout Design:

The layout design of DIO6012B regulator is relatively simple. For the best efficiency and minimum noise

problems, we should place the following components close to the IC: CIN, L, R1 and R2.

1) It is desirable to maximize the PCB copper area connecting to GND pin to achieve the best thermal and

noise performance. If the board space allowed, a ground plane is highly desirable.

2) CIN must be close to Pins IN and GND. The loop area formed by CIN and GND must be minimized.

3) The PCB copper area associated with LX pin must be minimized to avoid the potential noise problem.

4) The components R1 and R2, and the trace connecting to the FB pin must NOT be adjacent to the LX net on

the PCB layout to avoid the noise problem.