C2471
Datasheet
RDFC Controllers for Offline Applications up to 6 W
Product data
Page 4 of 18
DS-1639-0805
© Cambridge Semiconductor Ltd 2008
02-May-2008
PRINCIPLE OF OPERATION
Power-Up/Power-Down Sequences
The C2471 controllers are powered via their VDD pins. When mains voltage is first applied, a small amount
of current (IDDSLEEP) is drawn from the rectified mains input via high value start up resistors (Rht1 and Rht2 in
Figure 3). When the voltage on the VDD pin (VDD) reaches a level VOVDTHR the controller wakes up, demands
more supply current (IDDWAKE) and enters the Start-up state (see Figure 4). The controller stays in Start-up for
a short time during which internal circuit blocks are enabled and then changes to Active operation. In both
Start-up and Active states, the controller uses an internal shunt regulator to regulate the VDD rail voltage; the
regulator is disabled in Sleep. A higher regulation voltage is applied during Start-up (VDDREG(S)) than during
Active operation (VDDREG(R)) to help provide sufficient VDD before the Auxiliary supply from the transformer
rises to maintain VDD.
If the VDD pin voltage drops below VUVDTHR the controller goes back to Sleep, reducing the supply current
demand. The system will restart when input power is restored. To achieve a smooth power up sequence the
VDD reservoir capacitor needs to be large enough to sustain the supply above VUVDTHR over the Start-up
period.
Figure 4: VDD Pin Waveform (VDD) During Initial Power-up and Power-down
State
Description
Sleep
From initial application of power or from Active state if VDD falls below VUVDTHR, the
controller changes to Sleep state. Non-essential controller circuits are powered down
and the external switching transistor (Q1) is held off. Exit from Sleep state occurs when
VDD rises above VOVDTHR and the controller moves to the Start-up state.
Start-up
When the Start-up state is entered, internal controller circuits are activated and power
conversion begins (Standby mode – see Table 2). In Start-up the on-chip shunt
regulator stabilises VDD to an intermediate value, VDDREG(S). After a preset time, the
controller changes from Start-up to Active operation.
Active
Converter operation continues, the shunt regulator controls VDD to the lower VDDREG(R).
If VDD falls below VUVDTHR the controller ceases converter operation and reverts to
Sleep state.
Table 1: Summary of Low Power RDFC Controller States
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