
C2472, C2473 and C2474
Datasheet
RDFC Controllers for Offline Applications
Product data
Page 10 of 18
DS-1423-0709C
© Cambridge Semiconductor Ltd 2007
26-Sep-2007
IBASPBD is controlled by monitoring the voltage at the COL pin during T PBD; base current is increased
progressively as VCOL rises above threshold VCREF(see Figure 9). The desired on-state VCE of the switching
transistor is set by capacitors Cp and Ccol (see Figure 3), the COL pin capacitance (CINCOL) and VCREF.
V
C O L
V
C R E F
I
B A S P B D
Figure 9: IBASPBD characteristic
Power Control
Load conditions are sensed on a cycle-by-cycle basis via the CS pin. When low levels of output power
demand are detected, the controller progressively reduces the switching duty cycle to reduce power
consumption and to improve output voltage regulation. Power demand causes increase in duty up to the
maximum, or until Overload is detected.
The voltage at the CS pin is compared to two thresholds, one nominally a t GND voltage (VOCPL) to generate
an internal signal OCPL and the other at a negative threshold (VOCPH) to generate an internal signal OCPH.
The controller samples OCPL a short time (TOCPL) after turn-on of the primary switch. A negative voltage at
the CS pin indicates power demand so the controller increases the switching duty up to the maximum;
conversely a positive voltage causes a decrease in duty.
Excessive primary switch current, detected via OCPH, terminates the on -period of the primary switch to limit
power delivery (Overload mode). High levels of overload (when the converter output voltage held is low by
the load) causes OCPH to trigger soon after turn-on of the primary switch. This condition is detected by the
controller sampling OCPH at time TFBTHR after turn-on. If OCPH triggers within this time, the controller
changes to Foldback mode. To prevent mis-triggering, OCPH is blanked for a short period TCSBLANK after
turn-on.