RA2A2 datasheet(21/116 Pages) RENESAS

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Table 2.1

Absolute maximum ratings (2 of 2)

Parameter

Symbol

Value

Unit

Analog input voltage

When AN000 to AN003 are used

VAN

-0.3 to AVCC + 0.3

When ANINn and ANIPn (n = 0 to 6) are used

-0.6 to AVCC + 0.3*7

LCD voltage

VL1 voltage

VL1

-0.3 to +2.1 and -0.3 to

VL4 + 0.3

VL2 voltage

VL2

-0.3 to +6.5

VL3 voltage

VL3

-0.3 to +6.5

VL4 voltage

VL4

-0.3 to +6.5

CAPL, CAPH voltage *8

VLCAP

-0.3 to VL4 + 0.3*5

COM0 to COM7, SEG0

to SEG44, output

voltage

External resistance

division method

VOUT

-0.3 to VCC + 0.3*5

Capacitor split method

(VCC reference)

-0.3 to VCC + 0.3*5

Capacitor split method

(VL4 reference)

-0.3 to VL4 + 0.3*5

Internal voltage boosting

method (VL1 reference)

-0.3 to VL4 + 0.3*5

Internal voltage boosting

method (VL2 reference)

-0.3 to VL4 + 0.3*5

Operating temperature*2 *3 *4

Topr

-40 to +105

°C

Storage temperature

Tstg

-55 to +125

°C

Note 1. Ports P410 and P411 are 5V-tolerant.

When the ports are used as the IIC function, there is no problem even if the input pull-up power supply while the device is not

powered. However, the current injection that results from input of such a signal or I/O pull-up might cause malfunction and the

abnormal current that passes in the device at this time might cause degradation of internal elements.

Note 2. See section 2.2.1. Tj/Ta Definition.

Note 3. Contact Renesas Electronics sales office for information on derating operation under Ta = +105°C.

Derating is the systematic reduction of load for improved reliability.

Note 4. The upper limit of the operating temperature is 105°C, depending on the product.

Note 5. Must be 6.5 V or lower.

Note 6. This value defines the absolute maximum rating of AREGC, AVCM, and AVRT terminal. Do not use with voltage applied.

Note 7. The SDADC24 conversion target pin must not exceed AREGC +0.3 V.

Note 8. When using the internal voltage boosting method or capacitance split method, connect these VL1 to VL4 pins to VSS with a

capacitor (0.47 µF ± 30%), and connect a capacitor (0.47 µF ± 30%) between the CAPL and CAPH pins.

Caution: Permanent damage to the MCU may result if absolute maximum ratings are exceeded.

To preclude any malfunctions due to noise interference, insert capacitors with high frequency

characteristics between the VCC and VSS pins, between the AVCC and AVSS pins, and between the

VREFH0 and VREFL0 pins when VREFH0 is selected as the high potential reference voltage for the

ADC12. Place capacitors of the following value as close as possible to every power supply pin and use

the shortest and heaviest possible traces:

● VCC and VSS: about 0.1 µF

● VRTC and VSS: about 0.1 µF

● AVCC and AVSS: about 0.1 µF and 10 µF in parallel

● VREFH0 and VREFL0: about 0.1 µF

Also, connect capacitors as stabilization capacitance.

Connect the VCL pin to a VSS pin by a 4.7 µF capacitor. Each capacitor must be placed close to the pin.

● VCL and VSS: 4.7 µF

● AREGC and AVSS: 0.47 µF

● AVCM and AVSS: 0.47 µF

● AVRT and AVSS: 0.47 µF

RA2A2 Datasheet

2. Electrical Characteristics

R01DS0418EJ0130 Rev.1.30

Nov 8, 2025

Page 21 of 116

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