AS1130-BSST datasheet(47/67 Pages) AMSOSRAM

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[v2-01] 2016-Oct-12

AS1130 − Register Description

I²C Interface Monitoring Register (0x0A)

This register is used to monitor the activity on the I²C bus. If a

deadlock situation occurs (e.g. the bus SDA pin is pulled to low

and no communication is possible) the chip will reset the I²C

interface and the master is able to start the communication

again.

The time window for the reset of the interface of the AS1130

can be set via 7 bits from 256μs to 33ms. The default setting of

this register is 0xFF.

Figure 49:

I²C Interface Monitoring Register Format

CLK Synchronization Register (0x0B)

The default setting of this register is 0x00.

Figure 50:

CLK Synchronization Register Format

0x0A I²C Interface Monitoring Register

Bit

Bit Name

Default

Access

Bit Description

n/a

6:1

Timeout window

11111

R/W

Definition of the Timeout window (0 to 127 => 1 to

128 x 256μs)

0000000: 256μs

........

1111111: 32.7ms

i2c_monitor

R/W

0: I²C monitoring off

1: I²C monitoring on

0x0B CLK Synchronization Register

Bit

Bit Name

Default

Access

Bit Description

7:4

0000

n/a

3:2

clk_out

R/W

Adjustable clock out frequency

00: 1MHz

01: 500kHz

10: 125kHz

11: 32kHz

1sync_out

R/W

The internal oscillator is used as system-clk. The

selected clk frequency is available on pin D4 for

synchronization. (Output)(1)

0: Disabled

1: Enabled

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