DIO74559

Version 1.1, Oct 2024

www.dioo.com

© 2024 DIOO MICROCIRCUITS CO., LTD.

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Figure 4. RST/CLK voltage level translation architecture

Figure 5. I/O voltage level translation architecture

9.2. Input/output capacitor selections

Place a 100 nF capacitor with low Equivalent Series Resistance (ESR) in close proximity to the VCCA and VCCB

input terminals each. The preferred capacitor types are X5R or X7R multi-layer ceramic capacitors (MLCC) due

to their consistent value and ESR performance across temperature variations. The maximum ESR should be

under 500 mΩ (with a typical value being 50 mΩ).

9.3. Level shifter stage

The device eliminates the need for an additional input signal to control the direction of data flow between the

host and SIM. The control logic enables a change in driving direction only when both sides are in a HIGH state.

The first falling edge is recognized by the control logic, granting it control over the other signal side. In the event

of a rising edge signal, a one-shot circuit is employed to drive the non-driving output and accelerate the rising

edge. The internal logic of the device safeguards against communication errors or unforeseen incidents that

may drive both connected sides to be drivers simultaneously, thereby preventing a stuck-at situation. Once

released from being driven LOW, both I/Os will return to a HIGH level automatically.