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R7FA6T2AB3CFP Datasheet(PDF) 38 Page - Renesas Technology Corp

Part # R7FA6T2AB3CFP
Description  Renesas Microcontrollers
PDF  101 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

R7FA6T2AB3CFP Datasheet(HTML) 38 Page - Renesas Technology Corp

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Table 2.20
I/O ports, POEG, GPT, AGT, KINT and ADC trigger timing (3 of 4)
GPT Conditions:
High drive output is selected in the Port Drive Capability bit in the PmnPFS register.
AGT Conditions:
Middle drive output is selected in the Port Drive Capability bit in the PmnPFS register.
Parameter
Symbol
Min
Typ
Max
Unit
Test conditions
GPT
Input capture pulse width
Single edge
tGTICW
1.5
—
—
tPDcyc
Figure 2.23
Dual edge
2.5
—
—
GTIOCxY output skew (x
= 0 to 3, Y = A or B)
Middle drive buffer
tGTISK*1
—
—
4
ns
Figure 2.24
High drive buffer
—
—
4
High current output
buffer
—
—
4
GTIOCxY output skew (x
= 4 to 6, Y = A or B)
Middle drive buffer
—
—
4
High drive buffer
—
—
4
High current output
buffer
—
—
4
GTIOCxY output skew (x
= 7 to 9, Y = A or B)
Middle drive buffer
—
—
4
High drive buffer
—
—
4
High current output
buffer
—
—
4
GTIOCxY output skew (x
= 0 to 9, Y = A or B)
Middle drive buffer
—
—
6
High drive buffer
—
—
6
High current output
buffer
—
—
6
OPS output skew GTOUUP, GTOULO,
GTOVUP, GTOVLO, GTOWUP, GTOWLO
tGTOSK
— 
 
—
5
ns
Figure 2.25
External trigger input
pulse width
Synchr
onous
clock
Single-edge
setting
tGTEW
1.5
—
—
tPcyc
Figure 2.26
Both-edge
setting
2.5
—
—
Asynch
ronous
clock
Single-edge
setting
2.5
—
—
Both-edge
setting
3.5
—
—
Timer clock pulse width
Synchr
onous
clock
Single-edge
setting
tGTCKWH,
tGTCKWL
1.5
—
—
tPcyc
Figure 2.27
Both-edge
setting
2.5
—
—
Asynch
ronous
clock
Single-edge
setting
2.5
—
—
Both-edge
setting
3.5
—
—
GPT (PWM
Delay
Generation
Circuit)
GTIOCxY_Z skew (x = 0 to 3, Y = A or B, Z = A
to D)
tHRSK*2
—
—
4.0
ns
Figure 2.28
AGT
AGTIO, AGTEE input cycle
tACYC*2
50
—
—
ns
Figure 2.29
AGTIO, AGTEE input high width, low width
tACKWH,
tACKWL
20
—
—
ns
AGTIO, AGTO, AGTOA, AGTOB output cycle
tACYC2
33.3
—
—
ns
KINT
KRn (n = 00 to 07) pulse width
tKR
250
—
—
ns
Figure 2.30
RA6T2 Datasheet
2. Electrical Characteristics
R01DS0400EJ0150 Rev.1.50
Jul 2, 2025
Page 38 of 101



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