RX72N datasheet(127/179 Pages) RENESAS

127 / 179 page

R01DS0343EJ0120 Rev.1.20

Page 127 of 179

Nov 15, 2023

RX72N Group

2. Electrical Characteristics

Note:

tPBcyc: PCLKB cycle

Note 1. Cb is the total capacitance of the bus lines.

Figure 2.56

Simple IIC Bus Interface Input/Output Timing

Table 2.37

Simple IIC Timing

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr,

High-drive output is selected by the drive capacity control register.

Item

Symbol

Min.

Max.

Unit

Test

Conditions

Simple IIC

(Standard-mode)

SSDA input rise time

tSr

—

1000

Figure 2.56

SSDA input fall time

tSf

—

300

SSDA input spike pulse removal time

tSP

04 × tPBcyc

Data input setup time

tSDAS

250

—

Data input hold time

tSDAH

0—

SSCL, SSDA capacitive load

Cb*1

—

400

Simple IIC

(Fast-mode)

SSCL, SSDA input rise time

tSr

—

300

SSCL, SSDA input fall time

tSf

—

300

SSCL, SSDA input spike pulse removal

time

tSP

04 × tPBcyc

Data input setup time

tSDAS

100

—

Data input hold time

tSDAH

0—

SSCL, SSDA capacitive load

Cb*1

—

400

SSDA0 to SSDA12

SSCL0 to SSCL12

VIH

VIL

tSTAH

tSCLH

tSCLL

P*1

S*1

tSf

tSr

tSCL

tSDAH

tSDAS

tSTAS

tSP

tSTOS

P*1

tBUF

Test conditions

VIH = 0.7 × VCC, VIL = 0.3 × VCC

VOL = 0.6 V, IOL = 6 mA

Sr*1

Note 1. S, P, and Sr indicate the following conditions.

S: Start condition

P: Stop condition

Sr: Restart condition

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