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XRAG2 Datasheet(PDF) 10 Page - STMicroelectronics |
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XRAG2 Datasheet(HTML) 10 Page - STMicroelectronics |
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10 / 33 page ![]() XRAG2 memory mapping XRAG2 10/33 Figure 5. Three memory bank organization (EPC_length > 9d), memory map: 1. See Table 2 and Table 3 for description of EPC and ISO TID coding. 2.1 Tag identification (TID) structure The 64-bit TID memory content is written by STMicroelectronics according to the ISO 15963 Technical Report in order to follow the ISO 18000 standard recommendations. XRAG2 can be delivered with either ISO TID or EPC TID. Table 2 and Table 3 show the TID structure in each case. TID bank(1) EPC bank Reserved bank TID[63:48](1) TID[47:32] TID[15:0] TID[31:16] 30h 20h 10h 00h 3Fh 2Fh 1Fh 0Fh Kill password [31:16] Kill password [15:0] Access password [15:0] Access password [31:16] 30h 20h 10h 00h 3Fh 2Fh 1Fh 0Fh EPC[N:N-15] ... up to 256 EPC bits RFU EPC [15:0] 120h 110h ... 20h 12Fh 11Fh ... 2Fh (PC+EPC)length AFI/NSI CRC16[15:0] 10h 00h 1Fh 0Fh Bank 10 Bank 01 Bank 00 64 bits 304 bits 64 bits ai12310b ... ... ... ... ... ... Table 2. Structure of ISO TID b0 b1b2 b3 b4 b5 b6 b7 b8 b9b10b11 b12 b13 b14 b15 30h 42 bits 3Fh 20h ST 2Fh 10h 09h Reserved 1Fh 00h E0h 02h 0Fh |
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