PCF8534A datasheet(16/41 Pages) NXP

16 / 41 page

PCF8534A_0

Product data sheet

Rev. 00.90 — 4 February 2008

16 of 41

NXP Semiconductors

PCF8534A

Universal LCD driver for low multiplex rates

• In the 1:2 multiplex drive mode BP0 and BP2, BP1 and BP3 respectively carry the

same signals and may also be paired to increase the drive capabilities.

• In the static drive mode the same signal is carried by all four backplane outputs and

they can be connected in parallel for very high drive requirements.

7.10 Display RAM

The display RAM is a static 60

× 4-bit RAM which stores LCD data. A logic 1 in the RAM

bit map indicates the on-state of the corresponding LCD segment; similarly, a logic 0

indicates the off-state. There is a one-to-one correspondence between the RAM

addresses and the segment outputs, and between the individual bits of a RAM word and

the backplane outputs. The first RAM column corresponds to the 60 segments operated

with respect to backplane BP0 (see Figure 10). In multiplexed LCD applications the

segment data of the second, third and fourth column of the display RAM are

time-multiplexed with BP1, BP2 and BP3 respectively.

When display data is transmitted to the PCF8534A the display bytes received are stored

in the display RAM in accordance with the selected LCD drive mode. The data is stored as

it arrives and does not wait for the acknowledge cycle as with the commands. Depending

on the current MUX mode data is stored singularly, in pairs, triplets or quadruplets. e.g. in

1:2 MUX mode the RAM data is stored every second bit. To illustrate the filling order, an

example of a 7-segment numeric display showing all drive modes is given in Figure 11;

the RAM filling organization depicted applies equally to other LCD types. With reference

to Figure 11, in the static drive mode the eight transmitted data bits are placed in bit 0 of

eight successive display RAM addresses. In the 1:2 multiplex drive mode the eight

transmitted data bits are placed in bits 0 and 1 of four successive display RAM addresses.

In the 1:3 multiplex drive mode these bits are placed in bits 0, 1 and 2 of three successive

addresses, with bit 2 of the third address left unchanged. This last bit may, if necessary,

be controlled by an additional transfer to this address but care should be taken to avoid

overriding adjacent data because full bytes are always transmitted. In the 1:4 multiplex

drive mode the eight transmitted data bits are placed in bits 0, 1, 2 and 3 of two

successive display RAM addresses.

Table 6.

LCD frame frequencies

Frame frequency

Nominal frame frequency (Hz)

CLK

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