8SLVP2102_V01 datasheet(13/23 Pages) RENESAS

Part #	8SLVP2102

Description	Low Phase Noise, Dual 1-to-2, 3.3V, 2.5V LVPECL Output Fanout Buffer

PDF	23 Pages

Scroll/Zoom	100%

Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

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13 / 23 page

March 13, 2018

8SLVP2102 Datasheet

2.5V LVPECL Clock Input Interface

The PCLK /nPCLK accepts LVPECL, LVDS, CML and other

differential signals. Both signals must meet the VPP and VCMR input

requirements. Figures 3A to 3E show interface examples for the

PCLK/ nPCLK input driven by the most common driver types. The

input interfaces suggested here are examples only. If the driver is

from another vendor, use their termination recommendation. Please

consult with the vendor of the driver component to confirm the driver

termination requirements.

Figure 3A. PCLK/nPCLK Input Driven by a CML Driver

Figure 3C. PCLK/nPCLK Input Driven by a

2.5V LVPECL Driver

Figure 3E. PCLK/nPCLK Input Driven by a

2.5V LVDS Driver

Figure 3B. PCLK/nPCLK Input Driven by a

Built-In Pullup CML Driver

Figure 3D. PCLK/nPCLK Input Driven by a

2.5V LVPECL Driver with AC Couple

PCLK

nPCLK

LVPECL

Input

CML

2.5V

PCLK

nPCLK

2.5V

LVPECL

Input

PCLK

nPCLK

PCLK

nPCLK

2.5V

LVPECL

Input

2.5V

CML Built-In Pullup

8SLVP2102 Datasheet(PDF) 13 Page - Renesas Technology Corp