Application Hints (Continued)

When the voltage at pin 1 becomes too small to activate the

detector (k 14 Vp-p) the integrator is reset by Q3 after a

delay introduced by C18 A delay of 1 to 10 cycles of the

transmitted frequency is typical These integration and reset

delays as a function of the external component values are

shown in

Figures 13 and 14

Pin 16 provides a CMOS compatible logic output For driving

high-intensity displays pin 14 will sink up to 1A When driv-

ing a transformer such as T14 in

Figure 1 it is possible for

the primary current to integrate up to destructive levels un-

der conditions of multiple echo reception Pin 11 is em-

ployed to protect the power output (pin 14) C11 integrates

an internal current source while pin 14 is low When V11

reaches a 07V threshold the second gain stage is turned

OFF With the receiver OFF no signal will be applied to the

TLH7892 – 14

FIGURE 13 Integration

Delay vs C17

detector and pin 14 will turn OFF After another delay C11

is discharged and the receiver is then again activated With

C11 e 680 nF and a continuous echo return the receiver

will cycle ON and OFF every 6 ms This function can be

defeated by grounding pin 11

TYPICAL OPERATION

Figure 15 shows typical waveforms at pins 1 and 16 for

200 kHz operation with pin 9 left open The pin 1 oscillator

signal (5 Vp-p) lasts for 200 ms The next 900 ms show a

ring signal so strong that it is clipped by the receiver The

exponential nature of the decaying ring is seen for the next

500 ms An echo return appears at 39 ms Note that the

detector is held low during the transmit period and for the

duration of the ring

TLH7892 – 15

FIGURE 14 Integrator

Reset Delay vs C18

TLH7892 – 16

FIGURE 15 Typical TransmitReceive Waveforms

7